– Glen Brisebois and Arthur Alfred Roxas
Input capacitance can be a key specification for high impedance and high frequency operational amplifier (op amp) applications. Notably, when photodiode junction capacitance is small, the op amp input capacitance can dominate noise and bandwidth issues. The op amp input capacitance and the feedback resistor create a pole in the amplifier’s response, impacting stability and increasing the noise gain at higher frequencies. As a result, stability and phase margin could degrade and output noise could increase. In fact, some previous CDM (capacitance—difference mode) measurement techniques were based on high impedance inverting circuits and stability analysis, as well as noise analysis. These techniques can be quite tedious.
In a feedback amplifier such as an op amp, total effective input capacitance is comprised of CDM in parallel with the negative input common-mode capacitance, or CCM–, to ground. One of the reasons CDM is difficult to measure is that the op amp’s main task is keeping the two inputs from separating. Compared to the difficulty of CDM measurement, measuring positive input common-mode capacitance, CCM+, to ground directly is relatively easy. By putting a large series resistance in the noninverting pin of the op amp and applying a sine wave or noise source, the –3 dB frequency response due to the op amp input capacitance is measured using a network analyzer or a spectrum analyzer. CCM+ and CCM– are assumed to be identical, especially for voltage feedback amplifiers. However, measuring CDM has been more elusive through the years; various techniques used were dissatisfying due to the inherent nature of an op amp to force its inputs to be equal, bootstrapping the CDM. When the inputs are forced apart and current is measured, the output tries to counter. Traditional methods of probing CDM are indirect, relying on phase margin degradation and being complicated by other capacitances such as CCM– in parallel.
It is desired that the op amp under test be truly operational and functioning, as it normally would be under closed-loop conditions, just as customers use them. One possibility suggested was to split the inputs and let the output clip, but depending on the op amp topology, this could render internal circuitry nonoperational, so the measured capacitance may not reflect actual operational capacitance. In this approach, the inputs are not split too much to avoid nonlinearities in the input stage as well as excessive output swing or clipping. This article will present a simple and direct method of measuring CDM.
A New Way to Measure CDM
The authors decided to simply use a gain of 1 buffer circuit and excite the output and inverting input with a current source. The output and inverting input will move only as much as the op amp allows. At low frequencies, the output will move very little, so the current through CDM would be small. And at too high frequencies, the test may not be valid, nor the results useful. But at medium frequencies, where the gain-bandwidth of the op amp is falling but still not too low, the output motion could be adequate to provide enough voltage excitation and a measurable current through CDM.
The practically unlimited noise floor of LTspice® enabled a simple test simulation, shown in Figure 1. After seeing the technique work rather exactly in LTspice, the question became “will I have adequate SNR in the real world to make a good measurement?”
The angle is almost equal to –90°, which indicates that the impedance is capacitive. The 2 pF common-mode capacitances did not corrupt the measurement because CCM– is not in the path and 1/(2 × π × Freq × CCM+) >> 1 Ω.
Challenges: Finding the Right Equipment and Actual Test Setup
Looking at Figure 1, the 2 kΩ is put in series at the op amp output to transform the excitation from a voltage source to a current source. This will allow a small voltage in node “r,” which should be not too far from the voltage that will be seen in the noninverting pin of the op amp and will cause small current to flow in between the inputs for the CDM to be measured. Now, of course, the output voltage is small, being buffered by the device under test (DUT), and also the current in CDM is very small (57 nA in the sim), so measuring it using a 1 Ω resistor would be difficult on the bench. LTspice.ac and LTspice.tran simulations do not have resistor noise, but a 1 Ω resistor in the real world has 130 pA/√Hz and would render only 57 nV of signal from our anticipated 57 nA of capacitor current. Further simulations showed that replacing R1 with 50 Ω or 1 kΩ would not result in too much lost current into CCM+ at frequencies within the bandwidth of interest. For a better current measurement technique than a simple resistor, a transimpedance amplifier (TIA) could be used instead to replace R1. The TIA input would be connected to the noninverting pin of the op amp where the current is desired while fixing the voltage at virtual ground to preclude current in CCM–. It turns out that this is exactly how four-port impedance analyzers such as the Keysight/ Agilent HP4192A are implemented. The HP4192A can measure impedance over frequencies from 5 Hz to 13 MHz. Some of the newer pieces of equipment in the market that use the same impedance measurement technique are the E4990A impedance analyzer with 10 Hz to 120 MHz range and precision LCR meters like Keysight E4980A with 20 Hz to 2 MHz range.
Looking at the test circuit in Figure 2 below, the noninverting pin of the op amp is in virtual ground due to the TIA inside the impedance analyzer. Because of this, CCM+ would not affect the measurement since both of its terminals will be seen to be at ground potential. The small current developed across the CDM of the DUT will flow through the feedback resistor Rr of the TIA, which is then measured with the internal voltage meter.
Any four-port equipment that uses the autobalancing bridge1 impedance measurement method can be a good candidate to measure CDM. They are designed to generate a sine wave from an internal oscillator which is centered at zero with positive and negative swings for dual supply operation. If the op amp DUT is being powered in single supply, the bias function should be adjusted, so that the signal is not clipped against ground. In Figure 3, an HP4192A was used with the detailed connections going to the DUT.
Figure 4 shows the exact test setup used to achieve a very minimal parasitic capacitance contribution to CDM from the board and wiring. Any generalpurpose board can be used for slow op amps while high speed op amps demand stricter PCB board layout. The vertical grounded copper board dividers are placed to make sure to prevent the input and output from seeing additional field paths in parallel with the DUT CDM.
Results and Discussions
First, the board is tested without the DUT to measure its board capacitance. The board shown in Figure 4 was measured at 16 fF of DUT-less capacitance. This is a relatively small capacitance that can be neglected, as CDM values are typically expected in hundreds to thousands of femtofarads.
Most JFET and CMOS input op amps were measurable using this new CDM measurement technique. As an example, to illustrate the method, an LT1792 low noise precision JFET op amp was measured. The table below lists the impedance (Z), phase angle (θ), reactance XS, and the calculated CDM across a range of frequencies. Impedance exhibits a purely capacitive nature when the phase angle is –90°.
Table 1. LT1792 Impedance Measurement Across Frequencies at ±15 V Supply
Table 1 above gives results measured in the frequency range of 500 kHz to 5 MHz. The phase in this frequency range is close to being purely capacitive with a phase of –89° to –90°. Also, the reactance XS dominates the total input impedance such that Z ≈ XS. The averaged computed CDM is around 10.2 pF. Maximum frequency of measurement is 5 MHz because this part bandwidth is up to 5.6 MHz only. Results at lower frequencies became incoherent. This was presumably due to a quickly vanishing CDM current, with output voltage reduced by op amp action, while XS also becomes a higher impedance at low frequency.
The output of the op amp should also be checked at each step frequency to make sure that it is not being overdriven by the signal coming out from the impedance analyzer. The amplitude of this signal from HP4192A can be adjusted from 0.1 V to 1.1 V, just enough to create a wiggle in the output of the op amp and move the voltage level a little in the inverting input pin. Figure 5 shows a 28 mV peak-to-peak undistorted signal (green signal) at the output of the op amp at frequency equals 800 kHz. The yellow signal with 2.76 V peak-to-peak amplitude (1 V rms) is probed directly from the oscillating output port of the analyzer. It is arbitrarily decided not to allow distortion in the output, out of fairness, both to the DUT and to the HP4192A detectors. The probes were removed when getting the actual data of impedance and phase, although the setup is relatively immune to their effects.
A test was also done to measure CDM on a different supply voltage. The dependence of CDM on supplies and common-mode voltage may vary across different op amps; different topologies and transistor types are expected to result in different junction parasitics to high and low supplies. Table 2 shows the results for the ±5 V supply still with the LT1792. The average measured CDM is 9.2 pF, which is relatively close to the result of 10 pF with ±15 V supply. Thus, it could be concluded that LT1792 CDM does not change significantly by changing the supply voltage. This is in stark contrast to its CCM, which varies considerably with supply voltage.
Table 2. LT1792 Impedance Measurement Across Frequencies at ±5 V Supply
Meanwhile, bipolar input op amps are almost as straightforward compared to their FET counterparts. However, their high input bias current and current noise will be noticed, as these are in parallel with the CDM current. Added to that is the intrinsic differential resistance RDM inherent in bipolar differential pair inputs, also in parallel with CDM. Using ADA4004, a low noise precision amplifier as a sample, Table 3 shows the impedance measurements. Obviously, the phase does not indicate a purely capacitive behavior, as it is far from –90°. Although, the 4 MHz, 5 MHz, and 10 MHz frequencies are quite close, a parallel equivalent impedance RC model would fit this case, to be able to extract the CDM out of the other resistances. Therefore, parallel conductance GP, susceptance BP, and the calculated CDM across a range of frequencies are shown in Table 3, wherein CP is assumed to be equal to CDM.
Table 3. ADA4004 Impedance Measurement Across Frequencies at ±15 V Supply
Based on the results in Table 3, ADA4004 CDM can be estimated to be around 6.4 pF. The results also imply that across the frequency range presented in Table 3, CDM has some substantial parallel conductance GP and is not a purely capacitive CDM. The measurement is revealing the approximate 40 kΩ (1/ 25 μS) of real input differential resistance in this bipolar op amp.
Additional note: Attempts were made at measuring other types of op amps such as zero-drift op amps (LTC2050) and high speed bipolar op amps (LT6200). Results were incoherent, presumably because of switching artifacts in the zero-drift op amp and excessive current noise in the high speed bipolar op amp.
CDM is not a difficult measurement. One caveat is that the HP4192A reports an impedance in magnitude and angle. The capacitance reading assumes a simple series of RCs or parallel RCs, whereas op amp input impedance can be much more complicated. The capacitance reading should not necessarily just be taken at face value. Each op amp is also a unique case of its own. The frequency range wherein a capacitive reactance dominates the input impedance may vary from design to design. The input stage design, devices and processes used, Miller effects, and packaging could all contribute to the totality of the differential input impedance and its measurement. A JFET input op amp and a bipolar input op amp were measured, revealing both CDM and in the case of the bipolar input op amp, RDM results.
1 Gustaaf Sutorius. “Challenges and Solutions for Impedance Measurements.” Keysight Technologies, March 2014.
Glen Brisebois would like to thank Brian Hamilton for this challenge, Aaron Schultz and Paul Henneuse for their support, and Henry Surtihadi, Kaung Win, Barry Harvey, and Raj Ramchandani for their input.
Arthur Roxas would like to thank Paul Blanchard, Matt Duff, Jess Espiritu, and Kristina Fortunado for the opportunity to work on this project with Glen.
About the Author
Glen Brisebois is an applications engineer with the Signal Conditioning Group at Analog Devices in Silicon Valley. He attended the University of Alberta in Canada, achieving bachelor’s degrees in both physics and electrical engineering. He attempted monastic life for several years with both the Trappists and the Carthusians, but couldn’t stop thinking about circuits. He is now happily married with several children, and works a lot with circuits, but will sometimes advocate an ADC instead. His article “Signal Conditioning for High Impedance Sensors” at EDN magazine won the Best Article award of 2006. He can be reached at [email protected].
About the Author
Arthur Alfred Roxas is a product applications engineer for the Linear Products and Solutions Group. He joined Analog Devices in 2017. Prior to that, he worked for a Japanese semiconductor company doing design and layout. He graduated from University of the City of Manila with a bachelor’s degree in electronics and communications engineering and a master’s degree in electronics engineering major in microelectronics from Mapua Institute of Technology-Manila. He can be reached at [email protected]