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Renesas Develops New AI Accelerator Technology for Next-Gen AI Chips

Renesas Electronics has developed an AI accelerator that performs CNN (convolutional neural network) processing at high speeds and low power to move towards the next generation of Renesas embedded AI (e-AI), which will further accelerate increased intelligence of endpoint devices.

Renesas Electronics

A test chip from the company featuring this accelerator has achieved the power efficiency of 8.8 TOPS/W which is the industry’s highest class of power efficiency, the company said

The Renesas accelerator is based on the processing-in-memory (PIM) architecture, an increasingly popular approach for AI technology, in which multiply-and-accumulate operations are performed in the memory circuit as data is read out from that memory.

To create the new AI accelerator, Renesas developed the following three technologies.

  • First – a ternary-valued (-1, 0, 1) SRAM structure PIM technology that can perform large-scale CNN computations.
  • Second – an SRAM circuit to be applied with comparators that can read out memory data at low power.
  • Third – a technology that prevents calculation errors due to process variations in manufacturing.

“Together, these technologies achieve both a reduction in the memory access time in deep learning processing and a reduction in the power required for the multiply-and-accumulate operations. Thus, the new accelerator achieves the industry’s highest class of power efficiency while maintaining an accuracy ratio more than 99 percent when evaluated in a handwritten character recognition test (MNIST).” read the company release.

Renesas has now developed technologies that resolve the issues regarding the adequate accuracy of large scale CNN computation. The semiconductor company plans to implement these, as a leading-edge technology that can implement revolutionary AI chips of the future, to the next generation of e-AI solutions for applications such as wearable equipment and robots.

Key Features of the Newly Developed Technology for Next-Generation AI Chips:

  • Ternary (-1, 0, 1) SRAM structure PIM that can adjust its calculation bit number according to the accuracy required
  • High-precision/low-power memory data readout circuit that combines comparators and replica cells
  • Variation avoidance technology that suppresses calculation errors due to process variations in manufacturing.

Since introducing the embedded AI (e-AI) concept in 2015, Renesas has moved forward with the development of several e-AI solutions.

The new accelerator technology combines both low power consumption and improved computational performance and could be one of the key technologies to implement future class 4 applications.

The results were presented, on June 13, at the 2019 Symposia on VLSI Technology and Circuits in Kyoto, Japan, June 9-14, 2019.

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Jyoti Gazmer

A Mass Comm. graduate believes strongly in the power of words. A book lover who dreams to own a library some day. An introvert but will become your closest friend if you share mutual feelings about COFFEE. I prefer having more puppies over humans.

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