Cadence Design Systems has introduced the Cadence Integrity 3D-IC platform, the industry’s first comprehensive, high-capacity 3D-IC platform that integrates 3D design planning, implementation and system analysis in a single, unified cockpit.
The Integrity 3D-IC platform underpins Cadence’s third-generation 3D-IC solution, providing customers with system-driven power, performance and area (PPA) for individual chiplets through integrated thermal, power and static timing analysis capabilities.
“Cadence has historically offered customers strong 3D-IC packaging solutions through its leading digital, analog and package implementation product lines,” said Chin-Chi Teng, Senior Vice President and General Manager in the Digital & Signoff Group at Cadence. “With recent developments in advanced packaging technologies, we saw a need to further build upon our successful 3D-IC foundation, providing a more tightly integrated platform that ties our implementation technology with system-level planning and analysis. As the industry continues to move toward different configurations of 3D stacked dies, the new Integrity 3D-IC platform lets customers achieve system-driven PPA, reduced design complexity and faster time to market.”
“With 3D-IC design continuing to gain momentum, there is an increased need to automate the planning and partitioning of a 3D stack die system more efficiently. As the world-leading research and innovation hub in nanoelectronics and digital technologies and through our longstanding collaboration with Cadence, we’ve successfully found automated ways to partition designs to build an optimal 3D stack with increased accessible memory bandwidth that pushes performance and lowers power in advanced-node designs. The integrated memory on the logic flow included in Cadence’s Integrity 3D-IC platform enables cross-die planning, implementation and multi-die STA, which our research teams demonstrated on a multi-core high-performance design.” Said Eric Beyne, Senior Fellow and Program director, 3D System Integration, imec
“To push AI acceleration using optical computing, we’ve consistently leveraged all the latest, innovative trends in the chip design industry—a key innovation being multi-chiplet stacking. To build a heterogeneous multi-chiplet stacked design, it is important to have a fully integrated planning and implementation system, which can represent multiple technology nodes in a single cockpit. The Cadence Integrity 3D-IC platform provides a unified database solution with implementation and early system-level analysis capabilities, including timing signoff and electrothermal analysis. It helps us deliver next-generation innovation using optical computing for AI acceleration.” Said Ph.D Yichen Shen, Founder and CEO of Lightelligence Inc.
The platform uniquely provides system planning, integrated electrothermal, static timing analysis (STA) and physical verification flow, enabling faster, high-quality 3D design closure.