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Exclusive Interview – Cadence’s Cerebrus Offers a Revolution in Chip Design Productivity

Cadence’s Cerebrus Offers a Revolution in Chip Design Productivity Helping Semiconductor Industry to Delivering new SoC Product Features in this Connected World

Venkat ThanvantriTo enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in ML computer science, the next chip design automation revolution is now possible states Venkat Thanvantri | VP, R&D, AI/ML Digital and Signoff | Cadence while talking in an exclusive Interview with Niloy. In this most-awaited interview, the veteran underlines what’s changing design processes for the semiconductor industry and also the need for advanced technologies like AI/ML in their respective design strategies. Edited excerpts Below.

Let’s talk about how Cadence is extending Digital-Design leadership with stated revolutionary ML-Based Cerebrus?

Cadence’s Cerebrus Intelligent Chip Explorer utilizes massively distributed compute power and a unique machine learning (ML)-based reinforcement learning engine, combined with the Cadence digital full flow solution, to deliver better PPA more quickly. Cerebrus automation capabilities enable engineering teams to scale more efficiently and boost productivity so more designs can be implemented concurrently.

In addition to automated implementation flow optimization, Cerebrus has the capability to explore high-level design optimizations, such as dynamically resizing and shaping a floorplan to improve PPA much more efficiently than a manual approach. All design learnings are stored in a reinforcement learning model that can easily be used in future design projects to optimize the flow even more quickly.

Cerebrus offers a revolution in chip design productivity, which will allow the semiconductor industry to continue growing and delivering the new SoC product features and capabilities we all expect in our increasingly connected world.

What is driving the need for automating digital chip design integrating advance technologies such as (AI/ML)?

To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in ML computer science, the next chip design automation revolution is now possible.

The Cadence Cerebrus Intelligent Chip Explorer utilizes both of these technologies, based on the industry-leading Cadence digital full flow, to deliver better power, performance, and area (PPA) more quickly. Engineering teams now are able to scale and become more productive using the Cerebrus reinforcement learning engine to meet the challenges of increasingly large and more complex system-on-chip (SoC) designs.

According to you the key reason behind global chip shortage and how AI/ML can rev-up the semiconductor industry?

When Cadence talks about AI and ML in its software, we are talking about helping chip designers automate certain parts of the design process to speed time to market. The chip shortage has to do with manufacturing and has largely been attributed to a supply and demand gap, which is outside our domain.

How are the latest trends in India such as 5G, Industry 4.0, and automation processing build pressure on chip production?

The pressure on chip production is due to the increase in the demand for electronics – not just in India but across the world, and not just because of an increase in demand in the 5G and Industry 4.0 verticals, but also in other verticals such as automotive, hyperscale computing, Internet of Things (IoT), medical, aerospace, to name just a few.

How can chips be designed to be more PPA effective and produce sophisticated technology mechanisms?

Cadence’s Cerebrus Intelligent Chip Explorer is built on massive compute and machine learning architectures and utilizes the complete Cadence digital full flow solution. Cerebrus uses a unique reinforcement learning engine to deliver better design PPA results. By using a completely automated, machine learning-driven, RTL-to-GDS full-flow optimization technology, Cerebrus can deliver better PPA results more quickly than a manually-tuned flow, thereby improving engineering team productivity. Cerebrus uses the latest scalable distributed computing technology resources, either on-premises or in the cloud, to enable efficient and scalable chip implementation for the ever-increasing size and complexity of current SoC designs.

How do you see the shift from power to performance and area scaling in the role in the future?

Power, performance and area go hand-in-hand. That’s why the there is a dedicated acronym for it—“PPA”. It all boils down to the consistently increasing design complexity and size that we have seen in chips over the last decade or more. Chip designers are trying to optimize more and more functionality into a decreasing footprint. Change the area, and the power changes. Increase the performance, and the area and power change. Attempt to minimize power, and the area goes down—or up—depending on the optimization.

As chips scale in size and complexity, the interdependence of power, performance and area will only increase. All three are important considerations in chip design, with designers having to make tradeoffs between the three to optimize the chip.

What are the chip designs and technology propelling advanced demand of Automotive, Health, Mobile, Consumer, Communications, Industrial and Aero/Defence applications?

 We are seeing the following trends in the electronics industry today.

  • The Chip design industry is experiencing a renaissance. There is strong growth in 5G, autonomous driving, hyperscale compute, industrial IoT and other areas, which are underpinned with the application of artificial intelligence (AI) and ML.
  • New applications and technological interdependencies are generating demand for even more compute, more functionality, faster data transmission speeds. Today’s electronics have more chips in them with no end to this trend in sight.
  • As a result, next-generation chips must be produced faster and smarter. Engineers are overloaded and need support to keep up with demand. That is where ML in EDA comes into the picture.

In terms of semiconductor design, these trends are having impact on:

  • Traditional chip and package design EDA: Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, systems companies are increasingly designing their own semiconductor chips, and semiconductor companies are delivering software stacks to enable substantial differentiation of their products. Design size and complexity are increasing, with more designs on advanced process nodes. Other trends include 3D-IC and design for high-speed analog signals.
  • The system beyond the chip: Optimizing semiconductor devices for their targeted applications started in mobile devices and is now moving into cloud computing, automotive and other areas. Each application has different environmental conditions and constraints, requiring optimization of the silicon performance in the context of the system, as well as the system itself, across the boundaries of hardware and software, analog and digital, electrical, and mechanical.
  • Intelligence throughout: Many companies are introducing intelligent computation in their systems, which is creating a confluence of semiconductor design, system design and intelligent system design.

To power the technologies and products of the future, the world’s most creative companies require end-to-end solutions across chips, IP, packages, PCBs and systems to meet demanding design requirements and deliver extraordinary products. Cadence has evolved to address these changes and formulated its “Intelligent System Design” strategy in which it delivers world-class computational software capabilities across all aspects of electronics system design.

How would you define as it is said that Machine Learning can greatly shorten VLSI design times and later significantly alter the way VLSI design is done today.

The complexity of integrated circuits (ICs) means the number of possible design iterations that need to be evaluated continues to increase, but their regularity means design rules that work well can have a massive positive impact across large parts of the design. Using AI and ML to move from ‘maybe’ to ‘definitely’ in fewer iterative steps can deliver greater productivity in an automated flow.

The industry is in a constant state of development to expedite the design process. As fabrication processes shrink in dimensions, the ICs become commensurately more complex, and, as any design engineer appreciates, complexity increases the design cycle. That is true for any type of design. Designers are spending an enormous amount of time performing multiple tasks—for example, finding the best PPA and developing the optimal floorplan. To really shorten the design cycle, ML is paramount, providing the best path forward when it comes to improving productivity and design success.

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Niloy Banerjee

A generic movie-buff, passionate and professional with print journalism, serving editorial verticals on Technical and B2B segments, crude rover and writer on business happenings, spare time playing physical and digital forms of games; a love with philosophy is perennial as trying to archive pebbles from the ocean of literature. Lastly, a connoisseur in making and eating palatable cuisines.

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