CEA-Leti and Dolphin Design have collaborated to establish an adaptive back-biasing (ABB) architecture for FD-SOI chips that can be seamlessly integrated into the digital design flow with industrial-grade qualification, overcoming integration drawbacks of existing ABB techniques.
“The ABB development is a breakthrough for FD-SOI technology because it shows the first-ever results depicting the enhancement in the circuit performance after using ABB, and it will help increase performances and yields in FD-SOI designs,” said Gaël Pillonnet, a CEA-Leti scientist and an author of the paper, “A 0.021 mm² PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FD-SOI Technology.”
“The performances of our ABB IP are state of the art and show the compensation of the variations across process-voltage-temperature (PVT) conditions on a representative number of samples, enabling the usage of this solution in industrial products,” said Andrea Bonzo, IP program manager at Dolphin Design. “Previous efforts in this technique have reported only limited numbers of chips that perform as intended. With our technique, a large number of chips are shown to work properly. ABB is versatile and can be used to drive a large digital area without any limitation for any FD-SOI technology.”
Fully Depleted Silicon on Insulator (FD-SOI) is a technology that allows the biasing of the transistor’s body that acts as a back gate. Unlike conventional bulk technology, FD-SOI enables a wide voltage range of the body bias.
This permits compensating for process, voltage, and temperature (PVT) variations by controlling the threshold voltage.
Presented in a paper at ISSCC 2021, the new ABB technique also allows the application design to maintain a targeted operating frequency over a wide range of operating conditions such as temperature, manufacturing variability and supply voltage.
The architecture enables reducing the energy consumption of processors in 22nm FD-SOI technology by up to 30 percent and increasing the operating frequency up to 450 percent compared to a technique in which body biased technique is not used. It also improves the manufacturing yield.
With this new architecture, the ABB area is relatively small compared to the application design, and in both areas and power, it allows the application design to maintain its targeted speed (frequency) with relatively low overhead.