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Developers Save Time and Cost with TI’s extended “Jacinto 6” family, Enhances Portfolio of Auto infotainment Solutions

infotainment Solutions

Texas Instruments (TI) extends its “Jacinto 6” family of System-on-Chips (SoCs) with the commencement of an entry infotainment processor “Jacinto 6 Entry,” tailored for for display audio, radio/audio and other cost-sensitive in-vehicle segments. Developed on the same architecture of “Jacinto 6” devices, the new DRA71x processor enables automotive manufacturers to scale their investment without additional R&D or significant bill of material (BOM) increases to deliver a diverse portfolio of products with hardware and software compatibility.

The scalable performance within DRA71x is known to allow developers to target specific performance for their applications and leverage headroom using higher performance variants, if required, without software modifications or hardware changes.

“Jacinto 6 Entry”:  Differentiation and cost-optimization

The DRA71x “Jacinto 6 Entry” processor is the lowest cost, feature-optimized member of the “Jacinto 6” family, extending the DRA72x “Jacinto 6 Eco” processor into more cost-sensitive applications and systems. TI’s DRA71x delivers car manufacturers with unprecedented integration of automotive features and interfaces for a processor at the entry-level of infotainment systems. As a result, the BOM is reduced and software investments leveraging the “Jacinto 6” family are protected, including high-level operating systems such as Linux, QNX and Android on ARM Cortex-A15 cores, as well as DSP and other cores.

TI’s DRA71x delivers an optimized set of performance and features to address the display audio and entry infotainment segments including:

  • An integrated TMS320C66x DSP for software-defined radio (SDR) integration, audio/speech processing, noise suppression and camera/imaging processing
  • Video decode/processing capability with 1080p60 decoding at greater than 30Mbps to support concurrent high-quality smartphone screen replication (including 3-D maps) and on-board video acceleration for multimedia playback
  • Highest memory bandwidth at 32-bit DDR3 EMIF at 667 MHz for a best-in-class HMI, HD display support and improved auto concurrencies
  • Integrated video ports for integrating support for NHTSA-required rear-visibility technology or other camera applications
  • ARM Cortex-M4 cores as auxiliary processors to offload high-interrupt load tasks from the main ARM core and provide physical separation between High Level Operating System (HLOS)  and real-time operating system (RTOS)

Highly Scalable Family of Automotive Processors 

The “Jacinto 6” family of processors is built on the same architecture, offering software and hardware compatibility with the broadest array of highly scalable ARM Cortex-A15 cores for automotive applications. Other members of the “Jacinto 6” family of infotainment processors include:

  • The DRA72x, “Jacinto 6 Eco” delivering feature-rich, in-vehicle infotainment and telematics features for entry- to mid-level vehicles.
  • The DRA74x “Jacinto 6” is intended for mainstream in-vehicle infotainment applications and head-units.
  • Both DRA75x processors, “Jacinto 6 EP” and “Jacinto 6 Ex”, have extended DSP and vision processing performance to enhance digital cockpit integration.

The DRA71x “Jacinto 6 Entry” processor is intended for high-volume automotive manufacturers and is not available through distributors.


BiS Team

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