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Enabling Robust Wired Condition-Based Monitoring for Industry 4.0—Part 2


Richard Anslow and Dara O’Sullivan
Richard Anslow, System Applications Engineer and Dara O’Sullivan, System Applications Engineer

In the first part of this article, “ADM3066E a,” we presented Analog Devices’ wired interface solutions, which reduce customer design cycle and test time, and enable faster time to market for industrial CbM solutions. Several aspects were discussed, including selecting a suitable MEMS accelerometer and physical layer, as well as EMC performance and power design. In addition, three design solutions and performance trade-offs were presented in Part 1. This article (Part 2 of 2) focuses on detailed physical layer design considerations for the SPI to RS-485/RS-422 design solutions presented in Part 1.

Common challenges in implementing a wired physical layer interface for MEMS include managing EMC robustness and data integrity. However, when extending a clock synchronized interface such as SPI over long RS-485/RS-422 cables, along with combining power and data on the same twisted pair wires (phantom power), several additional challenges are presented. This article discusses the following key considerations and provides recommendations for designing the physical layer interface:

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