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How Commercial Parts Qualified for Space Applications can Help Save Power and System Cost

Organizations tend to seek lower satellite acquisition costs since they also need to consider factors such as faster revisit rates for earth observation imaging, which necessitates field constellations of satellites.

Ken O’NeillFor companies who purchase satellites, they are constantly sourcing for ever-increasing value from space assets. For instance, imaging satellites require features such as higher image resolution and faster frame rates. In addition, they require finer channel resolution as well as multiple channels for multispectral and hyperspectral imaging.

Designers face issues of constrained downlink bandwidth as they create imaging payloads with adequate resolution to meet satellite operator requirements. Consider a low earth orbit (LEO) imaging satellite generating tens of gigabits per second of data and orbiting the earth roughly 16 times a day. It is impractical for such a satellite to send a constant stream of data to the ground through a space relay network. Imagery data was previously compressed and stored on board of the satellite, however, by performing a larger amount of data processing, we can provide connection to the ground station using data relay network. This will allow information to be transmitted to the ground, as opposed to raw data. This has resulted in greater demand for components that not only have faster data processing, but also meet the stringent radiation tolerance requirements.

Advances in the artificial intelligence and machine learning (AI/ML) sector have made it easier to optimize the use of downlink bandwidth by tactics such as eliminating images that do not contain any useful information. For example, in a satellite monitoring land use, images where the ground is covered by thick cloud is of no use; or in a satellite tracking maritime traffic, images of the ocean with no ships seen are also of on value. AI/ML also enables automated decision-making on board the satellite, which can help reduce or eliminate human analysis and cut down latency to the deployment of imaging data.

With the changing space mission requirements, the demand for the latest space asset technologies continue to rise, but it is important to note that any products used in space must meet the basic requirements for sustainable and trustworthy operation.

Organizations tend to seek lower satellite acquisition costs since they also need to consider factors such as faster revisit rates for earth observation imaging, which necessitates field constellations of satellites. There are three key steps needed to prepare a commercial component for use in space applications: radiation assessment, packaging, and qualification.

Radiation Assessment

Radiation effects in space are prevalent and depend on the orbit. Any component destined for space must be assessed as any physical damages to the part may result in failure of operation of critical equipment of the satellite. Table 1 below concludes radiation effects in a variety of earth orbits.

Table 1: Radiation Effects in Earth Orbit.table

We can classify radiation effects in space into two main categories – total ionizing dose effects and single event effects.

Total ionizing dose (TID) refers to the long-term accumulation of radiation and causes performance to degrade and leakage current to increase in most microelectronic devices. In severe cases, TID may even result in a complete loss of functionality. Small variances in wafer fabrication process can impact TID effects. As a result, a per-wafer lot basis TID testing is often offered for microcircuits intended for space applications. A complete understanding of TID effects for the devices being flown is an important part of successful deployment of a microcircuit in space.

Single event effects (SEE) result from the interaction of a microcircuit with a single sub-atomic particle, which is typically a proton or heavy ion and in space applications, this is generally a neutron. SEE can be categorized as single event latch-up, single event upsets, single event transients and single event functional interrupts.

In a single event latch up, ionization caused by a heavy ion causes a parasitic PNPN structure to become forward biased. The levels of current may lead to permanent damage to the integrated circuit. Single event upsets occur due to the current pulse which results from the ionization and subsequent recombination of atoms of silicon when a heavy ion passes through a microcircuit. These happen in flip-flops and embedded memory elements. Designers have access to several forms of mitigation including triple modular redundancy (TMR) for flip-flops, and error detection and correction (EDAC) encoding and decoding for memories.

Single bit upsets in flip flops or embedded memory cells may have limited consequences. However, they can be catastrophic if they occur in the configuration memory of an SRAM-based FPGA. In such instances, unintended changes of functionality may occur in the FPGA due to a single heavy ion (Fig. 1). To reduce, configuration upsets, an extensive system overhead in the form of configuration scrubbing and repair is required.

fpgaSingle event transients refer to the transient changes in signals caused by single event radiation effects in combinatorial logic. They can be a cause for concern in the event that the transient is present at the data input to a register at exactly the moment the register is clocked. This causes the transient to be preserved as a single bit upset. The probability of capturing a transient increase with increases in clock frequency.

The term single event functional interrupt refers to any single radiation event that causes a change in function of an integrated circuit. With the growing sophistication of integrated circuits, the number of modes in which single event functional interrupts can occur increases significantly. A complete understanding of radiation effects for the devices being flown is crucial for the successful deployment of any microcircuit in space. As a result, organizations developing space-flight hardware must have test data for the exact wafer lot sourcing the flight parts. Assessments of radiation effects requires destructive tests. It is not possible to test flight units for radiation effects since it would severely impact the expected lifetime of the parts. Testing for TID effects is done on a sample basis for each wafer lot. Testing for single event effects is performed early in the product’s life due to single event effects’ dependency on the IC design and they tend not to be so variable with the wafer fabrication process. One needs to be extra cautious with commercial parts since any shipment of commercial parts may be sourced from different wafer lots. These may even be from different die revisions or even different foundries, which can dramatically increase the variability of radiation effects in the parts. To ensure that the parts examined for radiation testing are representative of the parts being flown, it is crucial to implement strict traceability. Microcircuits offered for space flight generally have complete lot traceability. Manufacturers of the devices can provide TID test data for the specific wafer lot sourcing the flight parts.


Microcircuits used in high-reliability satellites utilize hermetically sealed ceramic packages. One of the primary advantages is the inspect ability of ceramic packages. Military standards that govern the manufacturing and testing of components for utilization in space systems (for example Mil Prf 38534, Mil Prf 38535, and Mil Std 883 class B) requires third-party inspection of the integrated circuit in the package, before sealing the package. This enables the quality of the assembly to be verified. Inspection can be easily performed in ceramic packages prior to lid seal.

In extreme temperatures or in a vacuum, the ceramic material does not emit vapors, this is referred to as out-gassing. This is another advantage of ceramic packages. Plastic packages, on the other hand, can emit vapors that can cause fogging on optical components in space. Lastly, another advantage to note of is that hermetically sealed ceramic packages can protect the microelectronic component inside against ingress of harmful moisture or board-cleaning fluids during assembly and integration of space-flight hardware.

As a result, hermetically sealed ceramic packages are essential for the most stringent highest-level missions, such as national security space missions and human spaceflight missions.

As performance requirements continue to increase, there are growing and major challenges associated with ceramic packages. Unlike traditional packages such as ceramic quad flat packs (CQFP) where a linear arrangement of pins around the outside of the package is implemented, additional I/O pins needed by modern ICs requires that pins for signals, power supplies and ground are mounted in a 2D array on the underside of the package. Normal solder balls can shear as the PCB cycles through the extended temperature range due to the mismatch of thermal expansion coefficient between package and board resulting in mechanical stress. To address this problem, solder columns are used instead of solder balls. They are mechanically flexible and capable of absorbing the mechanical stress associated with the differing rates of thermal expansion of the board and ceramic package. The electrical properties related to ceramic packages pose an additional challenge as well. In the latest on-board signal processing systems that are being designed, there are serial data interconnectivity between ICs and between circuit boards with data rates reaching into the 10 to 12 Gb/sec range. While ceramic packages can keep pace with these needs, the next generation of systems will exceed these data rates which will be an issue for today’s ceramic package technology. To solve this issue, ceramic package suppliers are looking at new technologies that are under evaluation.

Given the challenges associated with ceramic packages, several space programs are planning to use integrated circuits with plastic packages. Plastic packages offer the advantage of lower electrical parasitic when compared to ceramic packages therefore resulting in higher performance in high speed I/Os. Moreover, since the coefficient of thermal expansion of plastic packages is much closer to that of the PCB material, it helps dramatically lower the mechanical stress on solder balls, which also eliminates the need for solder columns which promotes higher performance.


The type of testing performed during qualification of an IC for space is determined by whether the IC is integrated into a ceramic or plastic package. Ceramic-packaged ICs are qualified based on established standards such as Mil Prf 38535 or equivalent ESA specification. Most US-based suppliers will qualify to Mil Prf 38535. Main steps of the qualification are listed in table 1. Mil Prf 38535 specifies two levels of qualification, – QML class Q and QML class V. QML class Q is intended for high reliability defense applications, and QML class V is intended for the highest reliability space applications. The main difference between the two is that class V has the most stringent qualification requirements, such as a 4,000 hours high temperature operating life test for the qualification sample, whereas class Q has 1,000 hours. Microchip’s RTG4 radiation tolerant FPGAs, which achieved their QML class Q and QML class V qualifications in 2018 (Fig. 2) are examples of integrated circuits in ceramic packages.

microchipIntegrated circuits in plastic packages have no agreed-upon qualification standard in the space industry. In cases where plastic packages are offered for space applications, the qualification activities are based upon JEDEC standards. Major suppliers and consumers of ICs in the space industry are working together on the basis of a QML standard for the qualification and screening of plastic-packaged ICs for space use, that is in line with the framework of a JEDEC committee. Once a QML standard for space-grade qualification and screening of plastic encapsulated microcircuits is defined, IC suppliers that support spacegrade products are likely to offer microcircuits qualified and screened to that standard.

New Alternatives

With satellite service providers seeking to open new markets or create new capabilities such as global communication networks and high revisit-rate surface imaging, there is a need for constellations of satellites for these operations. To better manage the cost of deploying large quantities of satellites, satellite designers tend to use components that are not designed specifically for radiation environments or space deployment. However, commercial off-the shelf (COTS) components often do not come with space heritage, space qualification, or even traceability or homogeneity of wafer lots. As a result, radiation data gathered on one sample may not be representative of the parts destined for space flight.

To address this, several microcircuit manufacturers are offering radiation-tolerant components without the full set of QML space-level screening. For instance, Microchip’s RTG4 radiation-tolerant FPGA family is available in a plastic ball grid array package. A “Sub-QML” product such as this provides designers an alternative approach that eliminates QML screening to save cost. With radiation tolerant microcircuits, companies can enjoy a high level of assurance and radiation heritage for space missions, without the lack of traceability of COTS components.

There is a demand for high density, high performance integrated circuits to meet the evolving needs of space designers. The harsh nature of the space environment requires a high level of radiation tolerance and high level of reliability assurance. A well-defined set of qualification and screening requirements are essential for the success of future space missions, irrespective of whether plastic or ceramic packages are used. Established manufacturers of spacegrade microcircuits today offer an expanded range of products including traditional QMLqualified components and Sub-QML devices. These offer the benefits of radiation tolerance and traceability, in conjunction with lower cost packaging and screening.


BiS Team

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