Infineon Launches Thinnest Silicon Power Wafer for Efficiency
Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.
“The world’s thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology,” said Jochen Hanebeck, CEO at Infineon Technologies. “Infineon’s breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry’s innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN.”
This innovation will significantly help increase energy efficiency, power density and reliability in power conversion solutions for applications in AI data centers as well as consumer, motor control and computing applications. Halving the thickness of a wafer reduces the wafer’s substrate resistance by 50 percent, reducing power loss by more than 15 percent in power systems, compared to solutions based on conventional silicon wafers. For high-end AI server applications, where growing energy demand is driven by higher current levels, this is particularly important in power conversion: Here voltages have to be reduced from 230 V to a processor voltage below 1.8 V. The ultra-thin wafer technology boosts the vertical power delivery design, which is based on vertical Trench MOSFET technology and allows a very close connection to the AI chip processor, thus reducing power loss and enhancing overall efficiency.
To overcome the technical hurdles in reducing wafer thickness to the order of 20 micrometers, Infineon engineers had to establish an innovative and unique wafer grinding approach, since the metal stack that holds the chip on the wafer is thicker than 20 micrometers. This significantly influences handling and processing the backside of the thin wafer. Additionally, technical and production-related challenges like wafer bow and wafer separation have a major impact on the backend assembly processes ensuring the stability and first-class robustness of the wafers. The 20-micrometer thin wafer process builds on Infineon’s existing manufacturing expertise and ensures that the new technology can be seamlessly integrated into existing high-volume Si production lines without incurring additional manufacturing complexity, thus guaranteeing the highest possible yield and supply security.
