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Leveraging the Power of Silicon Carbide in Switched Power Converters

Author: René Mente, Senior Staff Engineer, Infineon Technologies


Much has been undertaken by the semiconductor industry over the past decades to improve on the parasitic components of silicon MOSFETs to meet the needs of switching converter designers. Through a combination of regulation and market demand for green technologies, these have resulted in a demand for products that can be used to build ever more efficient and compact power solutions. In the meantime, wide bandgap (WBG) technologies such as silicon carbide (SiC) have emerged that provide the improved parasitics switch-mode power supply (SMPS) designers are requesting. With the introduction of 650 V SiC MOSFETs to complement existing 1200 V discrete power devices, SiC becomes more attractive for applications for which they had not been previously considered.

As a result, SiC MOSFETs are increasingly being turned to in applications reaching into the kilowatt range, covering everything from power supplies for telecom and servers, to battery charging for the growing electric vehicle market. Their allure is linked to their superior robustness compared to their silicon counterparts, coupled with the ability to utilize them in hard-switched topologies of Continuous Conduction Mode (CCM) Power Factor Correction (PFC) designs which continuously uses the internal body diode. Furthermore, their support for high switching frequencies supports the industry’s drive towards smaller, more compact power converters.

No such thing as a free lunch

Of course, as is often the way, the benefits that SiC provides over Si devices are not provided ‘for free’, and there are some areas where SiC performs less well. This requires designers to take the time to fully understand the characteristics and capabilities of these novel new devices, as well as considering a move to new topologies. One thing should be clear: these devices are not drop-in replacements and using them as such may result in a loss in efficiency rather than a gain.

For example, the body diode of a CoolSiC™ device has a forward voltage (VF) that is some four times greater than that of a silicon CoolMOS™ device. Without adapting the circuit accordingly, a resonant LLC converter might actually see a drop in efficiency of up to 0.5% at light loads. Designers should also note that it is mandatory to boost through the channel and not through the body diode if the highest possible peak efficiency in CCM Totem Pole PFC designs are to be attained.

Another consideration is the thermal resistance, junction to case. Here CoolMOS provides a slight advantage with a value of 0.8 K/W (IPW60R070CFD7) against the 1.0 K/W of CoolSiC (IMW65R048M1H) on package level due to the smaller chip size of CoolSiC, although this thermal drawback proves to be negligible in actual designs.

On-resistance on par with silicon at operating temperature

Where designers see quick benefits is with parameters such as the on-resistance, RDS(on). CoolSiC sees a lower multiplication factor (κ) of around 1.13 against the 1.67 of CoolMOS at 100 °C. This means that at this typical operational junction temperature an 84 mΩ CoolSiC device achieves the same RDS(on) as a 57 mΩ CoolMOS device. This also highlights that simply comparing datasheet silicon and SiC RDS(on) does not provide the full picture. At the cold end of the temperature scale, CoolSiC provides further benefits over silicon devices due to its higher breakdown voltage, V(BR)DSS, resulting from its lower slope and dependency on temperature. This is useful in applications that are located outdoors or start up in low-temperature environments.

PowerPoint Presentation
Figure 1: The influence of temperature on RDS(on) is lower for CoolSiC than CoolMOS, resulting in a similar on-resistance at typical operational temperature.

CoolSiC MOSFETs can use the same EiceDRIVER™ devices as they have used to date in their silicon designs. However, it should be noted that, due to the difference in transfer characteristics (ID vs VGS), the gate (VGS) of these devices should be driven at 18 V rather than the typical 12 V used with CoolMOS. This delivers the RDS(on) as defined in the datasheet which lies some 18% below the on-resistance value achieved if the drive voltage is limited to 15 V. Should the design allow a new driver to be selected, it is worth considering a version featuring a higher undervoltage lockout of around 13 V to ensure that the SiC MOSFET and the system can safely operate under any abnormal operation conditions of the target application. Another advantage of SiC is the limited impact temperature has on the transfer characteristic between 25 °C and 150 °C.

PowerPoint Presentation
Figure 2: The transfer characteristics at 25°C (left) and 150°C (right) show a significantly lower impact for SiC devices than silicon MOSFETs.

Avoiding negative gate voltages

One area that requires attention is to ensure that the gate-source voltage is not allowed to become too negative. Ideally, there should be no negative turn-off voltage applied but, with the realities of practical circuits, this cannot be guaranteed unless it is considered during development and checked when prototyping. A VGS that reaches lower than -2 V and have a duration of more than 15 ns can result in a drift of the gate threshold voltage (VGS(th)) after end of life of the application. This can also result in an increase of RDS(on) together with a reduction in system efficiency over the lifetime of the application. One cause of negative VGS results from inductive-driven gate-source voltage oscillation at turn-off. This is a result of the high di/dt inside the gate drive loop over the source inductance. The second common cause is a capacitive-driven gate-source voltage at turn-on, originating from the high dv/dt switching of the second MOSFET in half-bridge configuration.

Such issues in silicon MOSFET designs are usually resolved by inserting a high-value resistor between the gate driver and the MOSFET gate or finding another way to slow the di/dt and dv/dt. Unfortunately, these approaches result in further switching losses and a resultant drop in system efficiency. When using SiC devices, the simple addition of a diode voltage clamp between the gate and source serves to resolve this challenge.

If the issue is purely inductive, splitting the common source to a power and driver source together with the clamp diode, and using any available Kelvin source, is the preferred approach. Use of a MOSFET with a Kelvin source is highly advisable in any high-current application. For example, in a 3.3 kW CCM Totem Pole PFC, turn-off currents can reach 25 A to 30 A. Use of the CoolSiC IMZA65R048M1H results in up to three-times lower EON losses over a device such as the IMWA65R048M1H that does not feature a Kelvin source.

PowerPoint Presentation
Figure 3: To avoid that the gate of a SiC MOSFET goes negative, a diode clamp, separate commons, and a Kelvin source should be considered.

Pushing beyond 99% efficiency

CoolSiC MOSFETs also have a higher output capacitance, COSS, than its silicon counterpart at drain-source voltages, VDS, above around 50V. This actually works to its advantage, resulting in reduced levels of overshoot during turn-off. For both device technologies the peak VDS, max is set at 80% of the datasheet limit. CoolMOS devices require a high gate resistor to achieve this requirement, resulting in the efficiency losses already mentioned, but CoolSiC designs can be implemented without such a resistor. This additionally simplifies the design and layout, together with their use. This achievable benefit is depending on the overall design parasitics designers can achieve.

The QOSS behavior of SiC technology also benefits hard and resonant switching topologies. With a 75% lower charge compared to silicon MOSFETs, less discharging is required, something that impacts Eon losses in CCM Totem Pole PFCs. And, while CoolMOS devices achieved a ten-times improvement in Qrr over the previous generation with the CFD/CFD7 family, CoolSiC attains a further five to ten-times improvement over this family in this parameter. This means, with the use of 48 mΩ devices, efficiencies of over 99% for a 3.3 kW CCM Totem Pole PFC can be attained where the best possible efficiency using CoolMOS in a Dual Boost PFC design peaks at 98.85%. And, despite the higher cost for SiC devices, the resultant reduction in bill-of-materials (BoM) between the two design approaches results in the SiC solution delivering a more cost-competitive 99% efficiency solution.

Figure 4: Even a 107 mΩ CoolSiC CCM Totem Pole PFC comes close to 99% efficiency, mostly outperforming the best CoolMOS dual boost PFC approach.


While advancements in silicon MOSFETs have attained remarkable improvements in their parasitic parameters over the years, the fundamental physics of silicon remains stubbornly in the way of further improvements. This limits the use of innovative new and simple topologies that can pave the way for sustainable green power initiatives. SiC, as has been shown here, also has its challenges in use and not every parasitic characteristic proves to be better than silicon. However, the advantages it does offer, coupled with its robustness in hard switching applications, make it worthwhile considering the most efficient power conversion applications. The introduction of the 650 V CoolSiC family enforces this, making SiC MOSFET technology more economically viable for those pushing power conversion to its limits.


BiS Team

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