Aldec has recently announced that InterMotion Technology has successfully completed the verification of its soft IP portfolio for the latest Lattice Semiconductor CrossLink FPGA family, using Active-HDL for mixed-HDL simulation and debugging.
Together with Lattice, InterMotion is in the process of completing the latest line of IP designs for the CrossLink FPGA family. The verification work on this development was greatly advanced by using Active-HDL Expert Edition with its powerful features and capabilities that gave InterMotion the ability to create, simulate and debug soft IP designs in a shorter time with improved quality of verification and reliability of codes.
“RTL and gate-level simulation, testbench generation, data flow and code coverage analysis are all complex and time-consuming parts of creating IP designs,” said Mick Fandrich CEO & Founder of InterMotion. “Active-HDL has allowed our engineers to take full advantage of Aldec’s top-quality HDL simulator for FPGA verification. The graphical design tools ensured quick Code2Graphics conversion, while the FSM Editor provided an easy-to-use tool for FSM design. The resulting increase in capacity and considerable reduction in time and efforts have allowed our company to meet our customers’ expectations for quality, schedule and price.”
InterMotion’s expertise covers FPGA product families such as Lattice’s low power ECP5, iCE40 UltraPlus, MachX02/3, CrossLink and CrossLink-NX. InterMotion has worked closely with Lattice engineering teams to develop more than 30 soft IP designs for their current and future FPGA product families. Products developed by InterMotion range from simple modules, such as GPIO and UART, to more complex designs, such as I3C, MIPI D-PHY, Byte-to-Pixel Converter, SubLVDS Image Sensor Receiver, SGMII, LPDDR2 and DDR3 memory controllers and Tri-Speed Ethernet MAC.
“FPGA design verification is one of our core-competencies, and we are known in the industry for the tool performance, reliability and support that we provide to FPGA engineers,” said Louie De Luna, Director of Marketing at Aldec. “Active-HDL was officially released in 1997 and continues to be the simulator-of-choice to verify soft IPs for FPGAs. We are pleased to support InterMotion with their technology contribution to Lattice CrossLink devices.”