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Meeting Solder Paste Printing Challenges for SiP in “Smart” IoT Devices

Authored by: Sze Pei Lim, Kenneth Thum, Andy C. Mackie, Ph.D, MSc, Indium Corporation.

Introduction

System-in-package (SiP) is an increasingly important package type that comprises a variety of assembly materials and processes that minimizes volume, without sacrificing computational intensity. This market is mostly being driven by mobile Internet of Things (IoT) devices, such as smartphones and smartwatches. Materials deposition techniques, especially solder paste printing, are also changing to match this need.

The development of ultra-fine solder powders and solder pastes began in the late 1990s, as the standard flip-chip assembly process of wafer/under bump metallization (UBM) solder bump, onto solder-on-pad (SoP) on the substrate became strongly established. The size and nature of the die-side flip-chip solder bump has also evolved, as illustrated in Figure 1.

Major changes in flip-chip solder deposition processes have taken place over the last 10 years, and are outlined in Table 1. The extensibility of solder paste usage for very fine-pitch solder bumps was originally believed to be pushing the need for even finer solder powder types such as type 8, and even a putative type 9—powder size distributions that are not even defined by IPC standards to this day (and Table 2). The extensibility was curtailed quite rapidly as fundamental limits of printability and reflow (especially voiding) made other solder bumping processes, especially plating, more favored.

Solder Paste and SiP

FIGURE-1
Figure 1. Flip-chip solder bump evolution.

Semiconductor assembly and packaging in SiP are driving the use of embedded devices, wafer-level chip-scale packaging (CSP), and similar space-saving techniques , while passive devices are also getting smaller and smaller. The adoption of 0201, 01005, and now even 008004 components (to be used in high-volume manufacturing (HVM) production in 2017) is underway, and these devices are, or are becoming, the norm in Figure 1. Flip-chip solder bump evolution.

Table 1. Flip-chip solder roadmapTABLE-1

Table 2. J-STD-005A definition of particle size distribution by particle diameter.TABLE-2

Challenges

Shrinking the final package size places constraints on the assembly materials and processes, some of which will necessitate major changes, as will be discussed in this section.

Solder Powder

As devices shrink, the size of the solder powder deposit must also shrink. A large deposit of solder paste can effectively be considered a continuum. However, as the deposit volume decreases, the finite size of the solder powder starts to become a problem, causing increases in the variability in the deposit size. The result of a simple analysis using an allowable variability of +/- n solder powder particles per deposit is shown in Table 3. This demonstrates, for example, that for a 100 micron diameter bump, with an allowable height variability of +/- 1.0%, a type 7 solder powder must be used (if the bump-to-bump variability is due to the number of particles per deposit varying by +/- 5 or more particles (print-to-print variation)).

Cleaning: No-clean Versus Water-Soluble Fluxes

It is no surprise that as devices get smaller and the footprint efficiency (total device area/package area) increases toward its 1.0 maximum (absent 3D packaging, of course), that cleaning is becoming more of a challenge. As we have shown previously, similar device and feature shrinkage is driving flip-chip assembly from water-soluble fluxes to ultra-low residue no-clean fluxes.

Table 3. Solder powder size effect on deposit size variance.TABLE-3

Paste Rheology and Printing

The rheology of the solder paste is critical; not only must the paste print consistently over a long stencil life, it must also print without slumping. This means it must have a yield stress greater than approximately 3N/m2 , which is still low enough to allow the paste to roll. It is also low enough to allow the paste to release from small apertures. A long stencil life necessarily reduces print to-print variability over time, and also maximizes the usage of the paste.

Solder Paste Testing

A detailed printing test was carried out to study the printing performance of different solder pastes. A test vehicle consisting of different pad sizes, and different gaps between two neighboring pads, was specifically designed for the printing test, which will be described in the next section.

Table 4. Solder paste types. TABLE-4

Table 5. Stencil openings and aspect ratios evaluated.TABLE-5

FIGURE-2
Figure 2. Outline of the print test vehicle.

Experimental

Four different solder pastes were used for the printing tests. The water-soluble solder paste is halogen-free, and the no-clean solder paste is ultra-low residue, having been specifically developed for tight-clearance SiP applications (Table 4).

The test vehicle is 237mm in length, 62mm in width, and 0.5mm thick. The land patterns are grouped into five columns, with gaps of varying sizes between pads, and three rows of different pad sizes. Each board has an array of two of these. The patterns are arranged in 0- and 90-degree orientation to simulate different directions of squeegee passes (Figure 2).

The test vehicle consists of three 008004 pads and one 01005 pad. In this study, however, we focused on the 008004 pads as shown below:

  • 125μm x 150μm
  • 100μm x 150μm
  • 112.5μm x 150μm
  • The gaps between pads are 50μm, 80μm, 100μm, 130μm, and 150μm

The pad metallization was a standard NiAu (ENIG). The stencil used was 50μm thick, laser-cut with a final electro-polish. The stencil aperture was designed to be 1:1 to the size of pad to be printed. The aspect ratios (AR) for the various stencil openings are shown in Table 5, where a DEK Horizon printer was used to deposit the paste, and a Koh Young SPI was used to measure print volume.

Results and Discussions

Gap Size Effects

Please note that bridging is observed for all the pastes with 50μm gaps between pads, hence the results for 50μm gaps are omitted in this paper. However, even with the nonoptimized printer setup condition, there is no problem printing all the pastes at gaps of 80μm and more. Future studies will focus on improving the printer clamping system and developing a support system for thin substrates and E-fab stencils to achieve better printing performance for 50μm gaps.

All paste print behavior is similar; a wider gap results in increased solder paste volume. The box plot in Figure 4 shows the volume vs. gap distance for paste D. This may be due to a stiffer stencil with a wider gap, therefore causing better solder paste release.

Solder Pastes

As shown in the box plot in Figure 3, pastes A and D perform better than pastes B and C, with reduced minima and higher volumes. We observed more paste insufficients with lower aspect ratios apertures.

FIGURE-3
Figure 3. Paste comparison on 0.68 AR pads (as example of data).
FIGURE-4
Figure 4. Example of paste D volume compared to different pad distances.
FIGURE-5
Figure 5. Comparison between different metal loading of paste D.

Metal Loading

In order to further study how the viscosity and rheology of a particular paste affect fine-feature print performance, a solder paste sample with 0.5% less metal loading than that used for paste D was prepared and printed. The results are shown in Figure 5. We observed that this apparently trivial reduction in metal load caused the average solder paste volume to increase. A two-sample T test was performed to investigate whether the results were statistically significant. A significance level of α = 0.05 and a P-value of 0 indicates that this was the case for 90.5% (much better), and 91% metal loading was statistically different, showing that 90.5% does perform significantly better than the 91% metal load.

Print Consistency

We also performed print process capability (print volume consistency) using Paste D with 90.5% metal loading, and the Cpk for various pad sizes are shown in Table 6. This further confirms that Paste D with 90.5% metal is capable of reliably and reproducibly printing 008004 components.

Reflow Testing

Reducing voiding in the final solder joint is an important consideration for mechanical reliability. Extensive studies were carried out to show that choosing the correct reflow profile could easily minimize voiding, and a more complete overview of these results can be found at [6].

Table 6. Cpk of different pads using paste D.TABLE-6

Future Technology Drivers

The future trend of discrete passive devices for IoT is uncertain. Some ceramic capacitor manufacturers, for example, have chosen not to develop 008004 and lower technology, resulting in a shrinking supplier base. At some point in the next five years, embedded passive devices will become favored, and at that point the need for increasingly finer solder paste for SiP will disappear. For the near term, this is clearly a trend, and many OSATs and contract manufacturers are investing in resources to make sure they are ready to deploy fine feature printing in the range of 100-120μm stencil opening for HVM.

About the author

Sze Pei LimSze Pei Lim is the Semiconductor Product Manager and is based in Malaysia. She manages the technical support team in the Southeast Asia region, which supports Taiwan, South Korea, Japan, Vietnam, Thailand, Malaysia, Philippines, Singapore, India, and Indonesia. Working closely with customers in the semiconductor and surface mount technology industries, she helps them optimize their processes, troubleshoots, and offers solutions. Sze Pei joined Indium Corporation in 2007. Prior to that, she was a research and development chemist. Her research included solder paste and flux formulation. She also worked as a technical manager for nine years at Inventec, where she provided technical support and managed testing in the lab.

Kenneth ThumKenneth Thum is Senior Technical Support Engineer for Indium Corporation and is based in Penang, Malaysia. Kenneth assists customers in northern Malaysia with troubleshooting issues, and provides technical support for Indium Corporation’s full product range. He has years of experience in leading teams of technicians to improve yields and supplier quality. Kenneth holds a bachelor’s degree from the University of Malaya in computer aided design and computer aided manufacturing. Additionally, he is an SMTA-certified process engineer.

Andy C MackiAndy C. Mackie, PhD, MSc, Senior Product Manager, Semiconductor and Advanced Assembly Materials, is an electronics industry expert in physical chemistry, surface chemistry, rheology, and semiconductor assembly materials and processes. He has more than 25 years of experience in new product and process development and materials marketing in aspects of electronics manufacturing from wafer fabrication to semiconductor packaging and electronics assembly.

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Nitisha Dubey

I am a Journalist with a post graduate degree in Journalism & Mass Communication. I love reading non-fiction books, exploring different destinations and varieties of cuisines. Biographies and historical movies are few favourites.

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