Mentor Graphics Corp. has declared that its IC design to silicon solution has achieved certification for TSMC’s Design Rule Manual (DRM) and SPICE model version 1.0 for its 16nm FinFET process.
The certification takes account of tools in the Calibre physical verification and design-for-manufacturing (DFM) platform, plus the Olympus-SoC place and route system, the Pyxis custom IC design platform, and Eldo SPICE simulator.
Mentor from its barrio also successfully demonstrated a complete 16nm FinFET digital flow using the Olympus-SoC and Calibre products and the ARM Cortex-A15 MPCore processor as the validation vehicle. The Mentor 16nm solutions are available now to support clienteles as they transition from test chips to full production 16nm FinFET design efforts.
The Olympus-SoC place and route system facilitates efficient design closure with complete support for all 16nm FinFET double patterning (DP), DRC and DFM rules, fin grid alignment for macros and standard cells, and Vt min-area rules support.
The fresh flow also supports low-voltage hold time fixing, interconnect resistance minimization, signal EM fixing, MiM Cap extraction to address timing impact, and enhanced pin accessibility and routability.
The Calibre nmDRC platform supports design teams to make sure that their designs meet process requirements. The SmartFill capability in Calibre YieldEnhancer, together with the other Mentor DFM products, Calibre LFD and Calibre CMPAnalyzer, were enhanced to be able to meet TSMC-specified requirements for filling, lithography, and CMP simulations for 16FF.
The TSMC 16nm design kit offering for Mentor affords reliability checks based on the Calibre PERCproduct. This empowers clienteles to analyze and correct issues like electrostatic discharge (ESD) and latch-up at both IP and full chip level using a common platform and set of checks regardless of the IP source.
To ensure accurate circuit simulation of FinFET devices, Mentor collaborated with TSMC on enhancement and certification of the high-performance Calibre xACT 2.5D and 3D extraction product, and FinFET device models in the Calibre nmLVS product.
The Pyxis custom IC design platform is extended to handle fin grids and deliver a fin grid display, and to support guard rings, MOS abutment rules and design rule-driven (DRD) layout. The Eldo simulator has been upgraded to provide accurate FinFET device and circuit level modeling based on the latest BSIM-CMG and TMI models from TSMC.
“We’ve worked closely with TSMC to ensure our tools are ready for 16nm FinFET technology, including ongoing efforts with TSMC to optimize Calibre rule decks for the best turnaround time,” alleged Joseph Sawicki, VP and GM of the Design to Silicon division at Mentor Graphics. Supplementing that – “By jointly evolving our products to handle 16nm FinFET requirements, we minimize the learning curve and allow designers to leverage TSMC’s offering to create differentiated value in their products.”
“The longstanding working relationship between TSMC and Mentor has allowed us to address the design requirements of 16nm FinFET, while continuing to deliver production ready solutions against an aggressive technology roadmap,” held Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. Rhetoricising that – “At each new node we are proving once again that ecosystem collaboration under Open Innovation Platform is critical to driving innovation for the semiconductor design industry.”