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Microchip Enters Memory Infrastructure Market

SMC 1000 8x25G enables high memory bandwidth required by next-generation CPUs and SoCs for AI and machine learning

Microchip Technology expands its data center portfolio and the company also announced to entry into the memory infrastructure market.

Microchip

To mark its augmentation in the memory infrastructure market, Microchip also rolled out the industry’s first commercially available serial memory controller.

The SMC 1000 8x25G touts to enable CPUs and other compute-centric SoCs to utilize four times the memory channels of parallel attached DDR4 DRAM within the same package footprint.

Microchip’s serial memory controllers deliver higher memory bandwidth and media independence to these compute-intensive platforms with ultra-low latency.

As the number of processing cores within CPUs has risen, the average memory bandwidth available to each processing core has decreased because CPU and SoC devices cannot scale the number of parallel DDR interfaces on a single chip to meet the needs of the increasing core count. The SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25 Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface. The result is a significant reduction in the required number of host CPU or SoC pins per DDR4 memory channel, allowing for more memory channels and increasing the memory bandwidth available.

The SMC 1000 8x25G is the first memory infrastructure product in Microchip’s portfolio that enables the media-independent OMI interface.

Microchip’s SMC 1000 8x25G Features:

  • An innovative low latency design that delivers less than four ns incremental latency over a traditional integrated DDR controller with LRDIMM.
  • This results in OMI-based DDIMM products having virtually identical bandwidth and latency performance to comparable LRDIMM products.

“Microchip is excited to introduce the industry’s first serial memory controller device to the market,” said Pete Hazen, vice president of Microchip’s Data Center Solutions business unit. “New memory interface technologies such as Open Memory Interface (OMI) enable a broad range of SoC applications to support the increasing memory requirements of high-performance data center applications. Microchip’s entrance into the memory infrastructure market underscores our commitment to improving performance and efficiency in the data center.”

SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin Differential Dual-Inline Memory Modules (DDIMM) with capacities ranging from 16 GB to 256 GB, conforming to the draft JEDEC DDR5 standard DDIMM form factor. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly plug into any OMI-compliant 25 Gbps interface.

Development Tools

To support customers building systems that are compliant with the OMI standard, the SMC 1000 comes with design-in collateral and ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive GUI.

Pricing and Availability

The SMC 1000 8x25G is sampling now. For additional information, visit: https://www.microchip.com/smartmemory. To order samples, contact a Microchip sales representative.

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Niloy Banerjee

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