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Never-Before Chip Design to Make Five Nanosecond Decision-Making

Computer scientists

With today’s chip design demands are complementing miniaturization and integrated electronics, Computer scientists has developed algorithms that control everything from unmanned aerial vehicles to desktop computers to the cellphones in our pockets.

But it can be complicated to match the code they develop to hardware systems that vary so widely.

“Each of these hardware architectures comes with its own programming environment, and you need a hardware expert who understands what’s under the hood so you can restructure your algorithms to overlap the target hardware architecture,” said Ali Akoglu, UA associate professor in the Department of Electrical and Computer Engineering and at the BIO5 Institute, director of the Reconfigurable Computing Lab and UA site director of the NSF Center for Cloud and Autonomic Computing. “Only then do you get optimal performance.”

Akoglu is collaborating with researchers from Arizona State University, Carnegie Mellon University and the University of Michigan, and from companies Arm, EpiSys and GDMS, to solve this problem by developing systems on chips, or SoCs, that allow software developers to focus their efforts on designing algorithms and applications, not on matching them to chip structures. They’re using a grant from the Defense Advanced Research Projects Agency, or DARPA—the UA portion of which is $820,000—to do it.

Designing for DARPA

These new chip-based systems won’t just automatically map software to hardware. DARPA wants researchers to design them to be “domain-specific” in order to strike a balance between efficiency and flexibility—that is, still able to complete more than one task, but not so generalized that they sacrifice speed or quality of functions for quantity.

They also must be able to incorporate new applications as technology advances. If a computer scientist develops code for a brand-new function—like sending holograms back and forth via text—the SoC should be able to map the software for that technology onto the hardware of the chip.

The team’s answer to DARPA’s challenge is a “domain-focused advanced software-reconfigurable heterogeneous SoC,” or DASH-SoC. It’s a mouthful, but the time spent saying it will be more than made up for in the months of work it could save computer scientists.

“When you bring in a graduate student to work with new hardware architecture, it takes three to six months for them to learn the programming environment, and another six months to optimize it,” Akoglu said. “When you consider this productivity problem, having a system interface that translates your code to target architecture at the push of a button is a very ambitious goal.”

While computer engineers like Akoglu create algorithms that everyone from heart surgeons to biologists use to improve their ability to predict outcomes, DARPA specifically wants systems for the domain of software radio, which includes applications ranging from cellphones to national security.

Five Tasks and Five Nanoseconds

There’s one more element that makes this new technology stand out: The DARPA grant stipulates that the SoC be able to run five applications at a time, which means balancing the demands of five different priorities as quickly and efficiently as possible. Like a student taking five classes that all involve completing a series of assignments, the chip has to do some careful planning and resource allocation to get each task done for each application.

This is the part of the project Akoglu and his collaborator Umit Ogras from ASU are leading: developing an intelligent scheduler that maps out which physical areas of the chip complete which tasks when. “Intelligent” here means that scheduler will improve over time via machine learning, the way a student might be better able to create an efficient schedule during senior year than freshman year.

“The intelligent scheduler will learn how to schedule the tasks for specialized processors and control the power needed to process them.” Ogras said. “As a result, we will deliver very powerful, energy-efficient and easy-to-use SoCs that can be used in a wide range of communications and radar applications.”

DARPA’s goal is an intelligent scheduler that takes only five nanoseconds for each decision. Chips with such intelligent scheduling technology don’t exist today, so creating them at all is ambitious—creating such a fast system adds an entirely different dimension, Akoglu said.

“That five nanoseconds business is giving me high blood pressure,” he joked. “But without setting these aggressive goals, we can’t push technology to the next level.”

The Article was Originally Published in PHYS.ORG


Niloy Banerjee

A generic movie-buff, passionate and professional with print journalism, serving editorial verticals on Technical and B2B segments, crude rover and writer on business happenings, spare time playing physical and digital forms of games; a love with philosophy is perennial as trying to archive pebbles from the ocean of literature. Lastly, a connoisseur in making and eating palatable cuisines.

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