As the number of cores jammed into a single chip flourishes, scalable power management strategies are needed to keep power under the standard limitations.
Researchers from Carnegie Mellon’s Department of Electrical and Computer Engineering and Washington State University have spotted a new approach to leverage energy-efficient multicore systems.
Taking on the same formula of wireless on-chip communication i.e. bypassing road congestion while on a long-route travel, researchers were able to provide an efficient communication backbone, which can be tailored for large scale multicore systems.
Voltage frequency islands (VFIs) have long been used to enable such strategies. In VFI-based designs, the system is partitioned into islands with individually adjustable voltage and frequencies so as to reduce the power within allowable performance penalties.
However, while enabling significant power savings, a main challenge of VFI-based designs is the on-chip communication cost which negatively impacts application performance. Indeed, mixed voltage/frequency interfaces must be used for inter-VFI communication, thereby increasing communication delay.
The researchers have demonstrated two innovative solutions, the first of which is through the VFI clustering methodology. A hybrid VFI clustering that combines both per-VFI utilization and inter-VFI communication enables minimal inter-VFI communication without greatly increasing the inter-cluster utilization variation. Secondly, researchers utilized a small-world wireless Network on Chip or mSWNoC to enable fast and energy efficient on-chip communication. The mSWNoC exploits small-world conThe wireless small-world connectivity is able to mitigate most of the performance penalties introduced by VFIs. Furthermore, VFI-based multicore systems with mSWNoC communication are shown to be significantly better in energy efficiency compared to classic systems using wired on-chip networks (e.g. mSWNoC improves the energy dissipation by 40% and the energy-delay product by 52% compared to a wireline mesh on common PERSEC and SPLASH-2 benchmarks).