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The Power Behind Vicor Packaging

EricQ: How would you characterize the evolution of Vicor within the power electronics domain, and what was the driving force of this evolution?

Vicor has been on the forefront of power delivery network (PDN) performance for decades by continually innovating on four essential technology pillars, spanning power delivery architectures, control systems, topologies and packaging.

Each pillar has multiple layers and all are essential to advancing the performance of Vicor power modules. However, the innovations in power system architecture, control systems and topologies would have little impact apart from the central pillar of packaging. Without innovating power module packaging technology, the industry-leading advances in power density, current density and efficiency could never be realized.

Power module packaging is a unique differentiator for Vicor and has been a core competency since the company’s inception. From its first Brick product to today’s ChiP™, Vicor has been continually innovating its packaging technology to deliver better solutions for power systems engineers.

Q: What was the genesis of the Vicor product portfolio in terms of power packaging?

Figure 1 — Vicor Maxi, Mini and Micro DC-DC Bricks revolutionized power systems design in the 80’s with a new high-power-density module package consisting of an overmolded board assembly mounted onto a baseplate for heat extraction.

Every innovation begins with a spark of an idea, of how technology can improve performance to better meet customer challenges. Sometimes innovations are ahead of the curve, and it takes time before early adopters comprehend the full potential of the innovation. This is what happened with the Vicor modular power component concept that brought the DC-DC converter module to market as a building block for designing advanced power system solutions in the 80s. Vicor modules were way ahead of the competition in terms of density and efficiency and they were packaged in a format that resembled a brick—hence the name Bricks. The Brick consisted of an overmolded circuit board assembly mounted onto a baseplate for optimal thermal management. This was a highly differentiated approach to power conversion, and Vicor Bricks drew interest from early adopters in the emerging communications, defense and industrial markets. Power system engineers realized that a decentralized, modular approach to their power system design would allow them to handle the increasing number of loads in their system and that Bricks had many advantages over bulky, centralized, multi-output power supplies. In fact, the advent of the Brick was key to the development and acceptance of distributed power architecture at the time.

This new power module provided a flexible, scalable solution which was essential for advanced power systems design. Vicor continued to drive the evolution of the Brick package by being the first to market with the Half-Brick and then in the 90s the first to offer the Quarter-Brick.

Q: How did Vicor power packaging progress from the original Brick package format, and what were the benefits?

Figure 2 – VI Chip® packaging was necessary to fully realize the breakthrough advances of the new FPA™ (Factorized Power Architecture) and advances in topologies and control systems.

In 2008 Vicor introduced three new innovations.

  1. A new architecture called FPA™ (Factorized Power Architecture)
  2. A new topology called SAC™ (Sine Amplitude Converter)
  3. ZVS and ZCS (zero-voltage and zero-current switching) control systems

Collectively they reduced power losses dramatically and drove a new package development, the VI Chip, initially in a one-inch-square package with a height just over a quarter of an inch, which could take full advantage of the improved efficiency and power density the three innovations.

The VI Chip packages were further developed as half, full and double sizes and were manufactured in individual cavities where their PCBs were fully overmolded with a thermally effcient molding compound. The VI Chip package had surface-mount J-lead pins or straight pins for though-hole mounting.

Q: How did manufacturing scalability factor into the next generation of Vicor power products subsequent to the VI Chip packaging?

Figure 3 – The new ChiP package was distinguished by its two-sided component assembly while being cut from fixed-size panels, similar to how silicon chips are made and cut from wafers.

In 2015 with further improvements in control systems, topologies, components and materials, the VI Chip® package was redesigned to capitalize on further power-loss reductions, higher-frequency control systems and topologies with resulting gains in power and current density. The new package was called the ChiP™ (Converter housed in Package), and although it looked similar to a VI Chip, its construction and manufacture was very different.

Instead of an individual cavity construction as in the VI Chip package, ChiPs are made and cut from a standard-size panel and full utilization is made of both sides of the module’s PCB for active and passive components. Thermal management of this package must take this into account with a double-sided cooling design to maximize performance and power density. Making and cutting ChiPs from panels is very similar to how silicon chips are made and cut from wafers, but whatever the power level, current level or voltage level of the module, ChiPs are all cut from the same panel size enabling a manufacturing operation that is very scalable. This advancement in package design and manufacturing offered significant advantages in terms of increased power and current density, plus high-volume automation and cost reduction.

Figure 4 The new panel manufacturing process was another innovation for the power industry. ChiPs are all cut from the same panel size enabling a manufacturing operation that is very scalable.

Q: To what extent did mounting configurability and thermal management considerations impact the evolution of the ChiP packaging platform?

ChiP packaging technology came under scrutiny again when Vicor advanced its innovations in control systems and topologies with a fourth generation (Gen 4) of power conversion and regulation ASIC controllers. The Gen 4 controllers enabled further advances in efficiency and power and current density. To take full advantage of the Gen 4 control silicon improvements in converter and regulator performance, the decision was made to retain the basic panel construction but with one difference: after completion of the molding process, the panel would be copper plated to provide terminal connections for power and signal pins.

Figure 5 – Following completion of the molding process, the panel of surface-mount CM-ChiPs is copper plated to provide terminal connections for power and signal pins.

The plating also enables thermally adept high-power front end AC or DC converter modules utilizing advanced cooling schemes. The new fourth-generation ChiPs advance performance significantly (see Figure 6) and keep Vicor on a track of consistently cutting power losses by 25% every 2.5 years.

Q: What are the core target applications for Vicor ChiP-packaged power products, and what are the key design challenges?

Figure 6 – The newest CM-ChiP packaging enables chassis mount, surface mount and pin-mount options

More recent innovations in ChiP packaging are enabling several new high-growth applications. One of the most demanding is advanced artificial intelligence (AI), where processor current levels have risen above 1000 amps. In these applications, power distribution losses in board and substrate copper power planes has become a dominant loss term and performance limiter. These applications require extremely high-current-density power modules that can be mounted as close as possible to the processor power pins to reduce these losses. Additionally, transient performance (di/dt) can also be affected by the impedance between the power module and the processor. This is a critical term when processor workloads are suddenly increased and immediate current draw is needed.

Figure 6 -Advances in power and current density enabled by cutting power losses by 25% every 2.5 years and advancing power module packaging technologies

To meet the requirements of these demanding applications, and minimize impedances it is necessary to deliver power vertically by positioning the power modules directly under the process and exactly matching the power modules’ output power pins with the power pin array of the processor. Typically, this would result in a board layout conflict because this is also the optimal location for the large number of bypass capacitors required for energy storage to meet instantaneous processor power demands.

Q: How can this ‘vertical power delivery’ architecture benefit from Vicor ChiP technology?

12The challenge of vertical power delivery (VPD) has been met with a ChiP stacking technology. The new VPD power modules consist of a current multiplier layer and a “gearbox” layer which holds the bypass capacitors and changes the pitch of the current multiplier to match the pitch and layout of the AI processor power pin map above. This new ChiP-stacking technology enables AI processor power system designers to deliver power in the most optimal way and to get the maximum performance out of their processor for high-performance computing (HPC) applications.

Figure 7- Vertical power delivery to advanced AI processors with stacked ChiPs reduces board and substrate power losses to improve processor performance

Q: How would you summarize the overall Vicor philosophy on power packaging?

The four pillars of Vicor innovation are completely intertwined, and each pillar has many elements and layers to it. Enabling the highest performing modular power delivery solutions and continually advancing power and current density demands that power module packaging is developed ahead of the delivery of control system, topology and architectural innovation advances. The Vicor ChiP packaging approach focuses on the miniaturization of every single component and element that makes up the module. As Vicor makes further improvements in performance, ChiP packaging will take on new levels of innovation, the journey is nowhere near over.


Niloy Banerjee

A generic movie-buff, passionate and professional with print journalism, serving editorial verticals on Technical and B2B segments, crude rover and writer on business happenings, spare time playing physical and digital forms of games; a love with philosophy is perennial as trying to archive pebbles from the ocean of literature. Lastly, a connoisseur in making and eating palatable cuisines.

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