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Microchip Reveals New SoC FPGA With Industry’s First RISC-V Architecture

Microchip Technology via its Microsemi Corporation subsidiary has extended its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs that combines the industry’s lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA).

PolarFire FPGA

Microchip’s new PolarFire SoC architecture was announced at the RISC-V Summit in Santa Clara, California. It brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. The PolarFire SoC architecture, developed in collaboration with SiFive, features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal and space-constrained applications in collaborative, networked IoT systems.

“The PolarFire SoC architecture is a compelling combination of low power, security, and reliability in a configurable device that brings real-time to Linux,” said Bruce Weyer, vice president of the Programmable Solutions business unit at Microchip. “Coupled with our robust Mi-V RISC-V ecosystem and Microchip’s extensive portfolio of system solutions, the PolarFire SoC architecture gives customers an excellent platform to meet computing’s next great challenges.”

PolarFire SoC includes extensive debug capabilities including instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors and FPGA fabric monitors, and Microchip’s built-in two-channel logic analyzer SmartDebug. The PolarFire SoC architecture includes reliability and security features such as single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA) safe crypto core, defense-grade secure boot, and 128Kb flash boot memory.

“As a fully customizable, programmable RISC-V platform, the PolarFire SoC architecture gives designers the freedom to create innovative Linux-based SoCs in a novel and interesting ways tailored for their distinct, domain-specific requirements,” said SiFive CEO Naveed Sherwami. “By leveraging SiFive’s market-leading U54-MC CPU core complex, PolarFire SoC will enable designers to overcome the universal challenge of building real-time systems with predictable behaviors.”

Development Tools

Evaluate and begin PolarFire SoC designs today using the antmicro Renode system modeling platform, which is now integrated with Microchip’s SoftConsole integrated design environment (IDE) for embedded designs targeting PolarFire SoCs. A PolarFire SoC development kit is also available now, consisting of the PolarFire FPGA-enabled HiFive Unleashed Expansion Board and SiFive’s HiFive Unleashed Development Board with its RISC-V microprocessor subsystem.

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