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sureCore Develops MiniMiser to Cut Register File Power Usage

sureCore has developed MiniMiser to cut register file power consumption in next-generation, battery-powered devices where extending recharge cycle times is paramount.

sureCore has expanded its power register files portfolio with MiniMiser that reduces the power consumption of register files by over 50%.

sureCore MiniMiser Register File PowersureCore has developed MiniMiser to cut register file power consumption in next-generation, battery-powered devices where extending recharge cycle times is paramount.

Tony Stansfield, sureCore’s CTO, explained: “Standard off-the-shelf Register File IP is usually based on the foundry bit cell, and whilst this gives optimal area utilization, the power metrics are often poor – with the bit cell itself precluding a reduction in operating voltage to tune the logic for a range of performance goals. Designers are forced to implement multiple power islands – at least one for the logic and one for the memories. This introduces a level of physical design complexity plus the addition of level shifters as well as necessitating considerable care with the timing analysis strategy. Our register file architecture readily supports both a wide operating voltage range as well as the capability to deliver the high performance needed by AI applications.” He went on to say, “sureCore has considerable expertise in this space and we have worked with some of the world’s leading companies who are exploiting this capability to utilize various operating voltages to deliver the performance needed by the application in a given mode.”

Paul Wells, sureCore’s CEO, concluded, “MiniMiser gives developers a new way of optimizing the power envelope for their design. Savings of over 50% can be delivered just by swapping in MiniMiser instances. By reviewing the application’s operational demands, they can further enhance this by introducing multiple performance modes tied to various operating voltages thereby ensuring the SoC is tuned to application needs without the usual design headaches mentioned above. As wearable devices have more and more AI built in to enrich the user experience and provide product differentiation, more memory will be needed to support the computing demands. Cutting their power use has become increasingly important in the quest to achieve a competitive power budget.”

sureCore first delivered an SRAM capable of similarly offering a wide operating voltage range over 4 years ago which developers have taken advantage of for identical reasons.

In that case, the memory is based on the foundry bit cell with the company’s patented SMART-Assist technology ensuring the bit cell is always operated in the foundry recommended voltage window.

The MiniMiser architecture is based on a customized storage element and exploits sureCore’s SRAM power-saving techniques to deliver significantly improved power characteristics even at nominal process voltages.


Aishwarya Saxena

A book geek, with creative mind, an electronics degree, and zealous for writing.Creativity is the one thing in her opinion which drove her to enter into editing field. Allured towards south Indian cuisine and culture, love to discover new cultures and their customs. Relishes in discovering new music genres.

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