By navigating our site, you agree to allow us to use cookies, in accordance with our Privacy Policy.

Synopsys red – carpets IC Compiler II

synopsys

MOUNTAIN VIEW, USA: Synopsys Inc. has rolled out IC Compiler II, a game-changing successor to its IC Compiler product, the industry’s current leading place-and-route solution intended for advanced design at both established and emerging nodes.

Built from the ground up on a completely novel, multi-threaded infrastructure, IC Compiler II introduces ultra-high-capacity design planning, unique clock-building technology and advanced global-analytical closure techniques. IC Compiler II ushers in a new era of productivity by facilitating a 10X increase in physical design throughout and is already contributing to successful tapeouts at leading clienteles.

Several of these clienteles will be sharing their experiences with IC Compiler II at the Synopsys Users Group (SNUG) Silicon Valley, opening at the Santa Clara Convention Center.

“From RTL synthesis to static timing to physical synthesis, Synopsys has a history of innovations that have transformed electronic design. With IC Compiler II, we are approaching another transformative juncture,” alleged Antun Domic, executive VP and GM of the Design Group at Synopsys.

Supplementing that – “Built from scratch for speed, and incorporating newly developed algorithmic approaches, this new solution offers un-paralleled improvements in throughput, opening the door to a world of new possibilities in physical design.”

Synopsys’ IC Compiler has long been acknowledged as the winning choice for advanced, high-performance designs at emerging, as well as established, silicon technology nodes. While unceasingly investing to ensure that IC Compiler remains state of the art, several years ago, Synopsys began building a fresh place-and-route system aimed at providing an order-of-magnitude leap in designer productivity.

This massive undertaking has been made possible by an asset mix unique to Synopsys: a deep resource pool to sustain parallel development efforts, advanced technical expertise to pursue fundamental advances in core algorithms and broad customer collaboration to make available feedback and to refine the new-fangled technology through use in actual designs. The result of this initiative is Synopsys’ newest place-and-route solution, IC Compiler II.

Synopsys from its barrio will continue to augment and support IC Compiler, providing flexibility for clienteles who wish to continue using it, and offering the possibility to move up to IC Compiler II at a time of their choosing.

IC Compiler II is a full-featured place-and-route system centered on a new multi-threaded infrastructure able to handle designs with more than 500 million instances. Exemplifying its “rethink, rebuild and reuse” development strategy, IC Compiler II relies on industry standard input and output formats, as well as familiar interfaces and process technology files, while introducing innovative design storage capability.

It was architected with a full chip-level focus from day one, deploying novel design planning capabilities that provide a 10X performance boost while consuming 5X smaller memory. This facilitates designers to quickly evaluate many floor-planning alternatives to be able to arrive at the right starting point for implementation.

PreviousComplementing these chip-level capabilities is the block-level functionality powered by a new global-analytical optimization engine, a completely new clock generator and unique algorithmic capabilities in post-route optimization, which together enable enhanced quality of results (QoR) in area, timing and power.

IC Compiler II also incorporates leading technologies used in IC Compiler, such as the conjugate-gradient placer and the ZRoute router. IC Compiler II achieves its results with an average of 5X faster runtime and 2X reduction in memory over the current solution. The combination of runtime speed-ups, superior floor plans, achievable QoR and an efficient, lightweight environment enables a reduction in design iterations, further boosting design productivity.

IC Compiler II has been built in close collaboration with some of the world’s leading design groups. Its initial shipment starts in mid-2014.

Tags

Jawed Akhtar

A Journalist by interest and a Music Enthusiast by passion. Wedded to Mother Nature, Jawed indulges his aesthetics in travelling and reading books of varied genres. Having covered News stories for top Dailies in his formative years, that is, he is game for tryst with Technology at Techmagnifier.

Related Articles

Upcoming Events