According to a news website, TSMC’s established 2nm project has made a major succeed. The research and development process is now in advanced stages. The company is optimistic that its risk trial production yield in the second half of 2023 can reach 90%.
TSMC established it last year to find a feasible path for development. Considering cost, equipment compatibility, technology maturity, and performance, 2nm adopts the MBCFET architecture based on the surround gate (GAA) process.
This solves the physical limit of FinFET’s current control leakage due to process shrinkage. TSMC previously revealed that its 2nm R&D and production will be in Baoshan and Hsinchu. It is also planning for four ultra-large wafer fabs from P1 to P4, covering an area of more than 90 hectares.
Looking at the current R&D progress of TSMC’s 2nm, it should enter risk trial production in 2023 and mass production in 2024
To continue the process of miniaturizing semiconductors, new technologies need to be introduced. The GAA (Gate-all-around, around the gate) adopted by TSMC 2nm is also called GAAFET. It has the same concept as FinFETs. The difference is that the gate of GAA wraps around the channel. According to different designs, GAA also has different forms. The current four mainstream technologies are nanowires, sheet-like structure multi-way bridging fins, hexagonal cross-section nanowires, and nanorings.