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Validate And Debug Your Digital Designs with the Right Testing

Test and measurement solutions to address the electronic circuit designers’ needs

-By Rohde & Schwarz India Team

RohdeToday’s world is driven by the latest industrial and economic technologies and trends such as IoT, Industry 4.0, and green energy on the one hand, and by fundamental changes in personal lifestyle such as e-health, e-mobility, smart homes, smart cities, and social media on the other hand. All these trends create a strong demand for a new generation of electronic devices that address the challenging requirements of wearability, mobility, connectivity, performance, power efficiency, robustness, and highest data rates.

Due to these demands, electronic engineers face more complex challenges than ever when designing and developing integrated board architectures. High-speed digital interfaces are at the core of all electronic designs. Increasing data rates and growing integration density create new challenges for designs at the IC, board, and system levels.

Signal integrity and power integrity are of fundamental importance in digital designs. Increasing data rates, shrinking supply voltages, and increasing integration densities require lower jitter and noise limits for signals and clocks. They also cause stronger impairments on the transmission channel like frequency-dependent loss, reflections, and crosstalk and increase the effects of voltage sag and ground bounce on the power rails. Additionally, shrinking supply voltages keep reducing power rail disturbance tolerances, inducing jitter and amplitude noise on signals and clocks.

The following range of test solutions are necessary for powerful validation and debugging of digital designs:
● Signal integrity: interface testing
● Signal integrity: PCB and interconnect testing
● Signal integrity: clock tree, PLL, and ADC/DAC testing
● Power integrity testing
● Protocol level debug testing

Signal Integrity: Interface test

Signal Integrity is essential for the correct functioning of all interfaces in your digital design. It is highly influenced by the transmitter and receiver implementation in the chip, as well as the design of the transmission channel, including PCB traces, vias, connectors, and cables. Eye diagrams provide an immediate insight to judge the quality of the signal. As Signal Integrity impairments are often pattern-dependent, a high acquisition rate is helpful to catch many acquisitions in a reasonable time and catch worst-case scenarios in the eye diagram. For further analysis and debugging, these tests are typically flanked by accurate measurement and decomposition of jitter and noise as well as TDR/TDT measurements on critical signal traces. Probing is key to getting good measurement results and de-embedding is used to remove the effects of the signal path between the probe point and test point and to get accurate results at the desired measurement plane. With real-time de-embedding, even triggering on the corrected waveform is possible.

R&s

Figure 1: Signal Integrity Interface Test

Signal Integrity: PCB and Interconnect test

Proper design of PCB traces, vias, connectors, and cables is essential to ensure Signal Integrity on the transmission channel. Performance is typically characterized by insertion loss and return loss as well as near-end crosstalk (NEXT) and far-end crosstalk (FEXT). Giving insights to a potential EMI or EMS coupling path, mode conversion like e.g. differential to common mode conversion is often specified and needs to be tested. Frequency domain parameters are also transformed into the time domain to view discontinuities and impedance over the signal structure as well as signal rise/fall time, intra-pair and inter-pair skew. Also, eye diagrams and eye mask tests are often performed based on the measured S-parameters.

To avoid a cumbersome TRM / TRL calibration with multiple standards, de-embedding is required to accurately characterize lead-ins and lead-outs to the DUT (device under test). With this, the lead-ins and lead-outs are removed from the measurement and accurate measurements of the DUT can be done. The characterized lead-in also can be used for de-embedding this signal path in an oscilloscope measurement.

Signal-integrity
Figure 2: Signal Integrity PCB and Interconnect test

Signal Integrity: Clock tree, PLL, and ADC/DAC test

The newest high-speed technologies require both, ultra-low jitter reference clocks as well as ultra-low jitter transmitter and receiver designs in the SoCs (System on Chip). New test methodologies are required, overcoming the limitations in the jitter measurement floor of existing methods and measuring the true jitter performance of a reference clock or SerDes PLL. This jitter performance also needs to be achieved in a real-life Power Integrity environment of a system design, with its power rail disturbances inducing jitter to the clock or SerDes PLL. This is typically characterized by the power supply noise rejection ratio PSNR. With the increasing complexity of high-speed technologies like 112Gbps Ethernet, ADC/DAC based equalization is being used and the corresponding analog-to-digital and digital-to-analog data converters need to be designed and characterized.

Clock-tree
Figure 3: Clock tree, PLL, and ADC/DAC test

Power integrity testing

The power delivery network (PDN) provides and delivers the required DC power to all active components on the board. As disturbances on power rails can cause serious impairments to the performance of the used ICs and the overall system, Power Integrity is a paramount requirement in board and system design.

A designer needs a wide range of tools to efficiently analyze unwanted disturbances on their power rails and identify their root cause. These powerful tools should help designers to verify the entire power delivery chain from the voltage regulator module (VRM) all the way to the supplied component.

Power-integrity-testing
Figure 4: Power integrity testing

Protocol level debug testing

Triggering wanted or unwanted protocol events is an important task in the verification and debugging of digital systems; both to analyze the system timing, and to detect protocol errors leading to malfunctions of the design. A fast and powerful trigger on protocol patterns, preferably even in real-time, is key to reliably acquiring all selected protocol events.

protocol
Figure 5: Protocol level debug testing

While selecting the right T&M solution partner, an electronic design expert needs to consider the following:
● Expertise in both the time and frequency domain
● Experience in working closely with the corresponding standardization bodies

Moreover, the right T&M solution provider should be able to provide a wide range of
● Signal Integrity solutions for interface tests, on the system- and on chip-level as well as to test PCBs and interconnects and to characterize lead-ins for use in oscilloscopes to de-embed from the measurement
● Powerful solutions to meet the new challenges in clock tree, SerDes PLL and ADC/DAC Test,
● Power rail test,
● Power delivery test,
● Real-time serial pattern triggering,
● Serial pattern triggering and decoding.

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BiS Team

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