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Why it’s tough to characterize SiC power MOSFETs

Switching transients and parasitics can combine to thwart the accurate measurement of important MOSFET operating parameters.

– LEVI GANT Xuning Zhang, Ph.D., Littelfuse, Inc


Silicon carbide (SiC) power MOSFETs get a lot of attention because they can switch fast while maintaining high blocking voltages. But their superior switching qualities also have potential drawbacks. Parasitic inductances caused by lessthan-optimal board layouts, along with the SiC MOSFET’s fast dv/dt and di/dt qualities, can create voltage and current overshoot, switching losses, and system instability problems. To head off such difficulties, designers must understand SiC MOSFET switching qualities in depth.

Additionally, the extremely fast switching speeds of SiC MOSFETs also present challenges when characterizing the devices. For example, equipment selection can affect test and measurement accuracy. The highly sensitive design and integration schemes of the driving and power stages also play a role in minimizing voltage spikes, EMI, and switching losses.

Ensuring test and measurement accuracy

Circuit and package parasitics and the high-speed switching of SiC MOSFETs all complicate characterization tasks. The fast dv/dt and di/dt amplify measurement inaccuracies, voltage/current ringing, etc. High dv/dt can produce large transient voltage spikes, as well as common-mode noise that can appear as damped oscillations. High di/dt generates noise that can couple with nearby magnetic fields. These effects can be difficult to measure and diagnose. It takes special tools and test methods to uncover hidden problems before they emerge during product qualification stages or as infant mortality failures. And it takes tools with exceptional bandwidth and dynamic range to characterize SiC power devices that are switching high levels of power at high speeds.

Differential probes are commonly used for high-voltage measurements of this type. But though they offer built-in galvanic isolation, they have relatively limited bandwidth. In contrast, passive voltage probes have enough bandwidth but lack galvanic isolation. Additionally, many passive voltage probes are not rated for high voltages. If this is the case, a traditional voltage divider must be designed into the circuit as well, introducing another resistive load. All things considered, the best option for these voltage measurements is a passive voltage probe with a voltage rating high enough to capture high dv/dt transients. Four methods are commonly used for measuring current: a Rogowski coil, an active current probe, a current transformer, or a coaxial current shunt. Each method presents both pros and cons. For example, an active current probe and a Rogowski coil are unobtrusive in terms of incorporating them into the test circuit. However, they typically lack the bandwidth to measure current ringing effects.

A current transformer likely has enough bandwidth to capture ringing frequencies. But it requires that current pass through its aperture – sometimes a tight bottleneck — and can’t make dc measurements, a drawback it shares with the Rogowski coil. The current shunt also requires a bottleneck in the circuit and is not galvanically isolated like the other three options. But it is often the best way to measure current during characterization because it captures all frequencies, from dc up to megahertz. It should be noted, however, that the current shunt has a low power dissipation. So it is only appropriate for measurements in pulsed tests and not for continuously operated systems.

Optimizing power loop layout

Most power circuits actually contain two main circuits: the gate drive loop and the power loop. In the power loop, high levels of voltage and current switch at extremely fast edge rates. This phenomenon leads to voltage and current overshoot and ringing. The extent of overshoot and ringing relates to the amount of parasitic inductance and capacitance in the power loop.

One primary concern is voltage overshoot during turn-off. This overshoot is characterized by the product of the di/ dt and power loop inductance. A high di/dt is desirable, so designers must keep the power loop inductance as low as possible. Peak-voltage overshoots that approach the device’s maximum voltage rating put the device at greater risk of catastrophic failure. If excessive parasitic inductance in the power loop can’t be avoided, designers could be forced to limit the speed at which the devices switch or to implement a multi-level topology, at the cost of greater design complexity and more components.

Another concern is electromagnetic interference. During switching, severe ringing in the current waveforms can turn the power loop into an antenna, broad casting megahertz – band frequencies. This noise broadcast by the power loop can potentially couple into other sub-circuits, perhaps causing inadvertent device turn-on and shootthrough, nearby peripheral circuit malfunctions, or failure to comply with mandated electromagnetic compatibility regulations.

The first principle of optimizing the power loop layout should be to keep the board compact and simple, minimizing the overall power loop area. The ideal scenario would be a loop that consists of only one point in space, that is, no trace/ wire at all. A more realistic scenario is a loop with an outgoing path that overlaps with (is mirrored by, on another PCB layer) the return path, a practice known as lamination. In portions of the loop where lamination is not possible (such as the pins of a through-hole component), power paths should be wide enough to accommodate the current but as short as possible to maintain a compact overall loop.

The use of decoupling capacitors is another good practice for optimizing the power-loop layout. The process of switching at high speeds creates higher-order harmonics of the switching frequency (fs) and transient-related frequencies (ftrans) that extend well into the megahertz range. Typically, the dc link capacitor acts as a notch filter, eliminating oscillations corresponding to fs and its harmonics of appreciable amplitude; however, it does not suppress ftrans frequencies, which can couple into neighboring traces and circuits. To suppress peaks associated with ftrans, connect relatively high-farad film capacitors across the dc link and place them as close to the power transistors as possible to minimize the associated loop inductance.

Gate driver design

The gate drive has two main purposes: to turn power switches on and off in a stable, well-controlled manner and to protect power stages when necessary. However, these tasks can be difficult without proper design layout and integration of the gate drive with the power stage. Common problems include unnecessary switching losses, gate-voltage overshoot and ringing, and EMI from the power loop that makes the control circuit malfunction.

Even a modest level of common-source inductance (LCSI) will resist fast changes in current and boost switching losses. In the presence of high gate and source loop inductance (LG and LS), high values of di/dt can lead to overshoots in the voltage that appears at the device gate. Oscillations in the gate voltage waveform can lead to inadvertent turn-on and, as a result, potentially catastrophic shootthrough events. Hammering the device gate repeatedly with excessive voltage can also degrade device reliability and lifetime.

Double-Pulse Test Setup

Best practices to optimize the design and integration of the gate driver circuit include reducing the effect of inductive coupling between the gate and power loops. Wherever possible, place these two loops in orthogonal planes. Next, just as with optimizing the power loop, minimize the total gate loop area through a combination of lamination and shortening of path lengths. Finally, to reduce common-source inductance, decouple the gate and power loops by using packages with a dedicated Kelvin source, such as the four-lead TO-247 or the seven-lead TO-263.

Double-pulse testing offers a way to evaluate a SiCdevice’s switching performance accurately on a per-cycle basis. This test involves turning the device on twice.

A double-pulse test setup. In this test, an inductive load is in parallel with a free-wheeling device in the upper switch position. These elements make up the free-wheeling path for current during DUT turn-off states. The DUT occupies the lower switch position. This testing configuration is useful for studying switching energy and gate charge characteristics of the DUT.

The width of the first turn-on pulse, in conjunction with the inductor value and bus voltage, determines the current amplitude through the device during turn-off. During the period between the first and second turn-on pulses, the energy stored in the inductor circulates through a free-wheeling device. This action allows the device to see the same set of operating parameters during the rising edge of the second pulse, the turn-on event.

In a double-pulse test, an inductive load is placed in parallel with a free-wheeling device in the upper switch position. These elements make up the free-wheeling path for current during DUT turn-off. The DUT occupies the lower switch position. This testing configuration is useful for studying switching energy and gate charge qualities of the DUT. The waveforms of interest are gate-source voltage (VGS), drain-source voltage (VDS), and drain current (ID).

VGSIn this test, voltage-controlled relays disconnect the dc power supply (positive and negative rails) from the test setup. The dc link capacitance is sized so it can maintain the desired bus voltage throughout the test after being disconnected from the dc power supply.

This improves measurement conditions by minimizing the risk of ringing during transient events caused by ground loops. If the system can’t accommodate a dc link capacitor big enough to allow for disconnection from the dc voltage supply, the dc link capacitance must still be large enough to maintain dc voltage during device switching.

Results of a double-pulse test performed with an 800-Vdc bus voltage and a device current of 20 A. Top, captured waveforms from double-pulse test (10 μsec/div). Middle, magnified portions of the waveforms above that correspond to the turn-off transient waveforms (50 nsec/div). Bottom, magnified portions of the top waveform that correspond to the turn-on transient waveforms (50 nsec/div). These events are used to characterize the switching behavior of the MOSFET in terms of its switching energy, switching speed, rise and fall times, voltage overshoot, etc.

The high switching speed of SiC MOSFETs means the dv/dt and di/dt can exceed 80 V/nsec and 5 A/nsec respectively under certain test conditions. Because these devices are switching on and off within tens of nanoseconds, the measurement probes must have adequate bandwidth, good dynamic performance, and loading capacitance that is small.


Matlab is a useful tool for determining the numerical values of device switching qualities. Once the raw data is imported, the VDS and ID must be properly deskewed. A nearby graphic gives an example of plots generated for the turn-on and turn-off transient voltage (VDS), current (ID), and instantaneous power. Switching energy calculations and switching behavior of the DUT can be derived from these waveforms. The waveforms indicate that, during the turn-off event, a ~70-V overshoot takes place, dv/dt = 68.72 V/nsec, di/dt = 1 A/ nsec, and turn-off loss is ~60 μJ. During the turn-on event, a ~10-A overshoot takes place, dv/dt = 39.47 V/nsec, di/dt = 5.2 A/nsec, and turn-on loss is ~270 μJ. Note that switching loss values are obtained via integration of instantaneous power. The double-pulse technique has proven useful for characterizing SiC MOSFET switching losses, as well as for other typical dynamic parameters such as switching times, gate charge, and reverse recovery.


An application note covers the Littelfuse Dynamic Characterization Platform: Double-pulse test waveforms after postprocessing.


BiS Team

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