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Xilinx Pilots Ultra High Productivity to Mainstream System & Platform Designers


Xilinx enables a new ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms through its new launch of Vivado Design Suite HLx Editions. These new HLx Editions include HL System Edition, HL Design Edition and HL WebPACK Edition.

All HLx Editions include Vivado High-Level Synthesis (HLS) including C/C++ libraries, Vivado IP Integrator (IPI), LogicCORE IP subsystems, and the full Vivado implementation tool suite to enable mainstream users to readily adopt the most productive and advanced C and IP-based design flows.

When coupled with the new UltraFast High-Level Productivity Design Methodology Guide, users can realize a 10-15X productivity gain over traditional approaches. The HLx Edition is available as a no-cost upgrade to the Vivado Design Suite.

Ultra High Productivity for Creating and Programming Reusable Platforms

To realize C and IP-based design technologies and methodologies productivity, customers are known to adopt all or a subset of the following; 1) C-based design and optimized reuse, 2) reuse of IP subsystems, 3) integration automation, and 4) accelerated design closure.

The HLx Editions include Vivado HLS, Vivado IPI, LogicCORE IP subsystems, and the full Vivado implementation tool suite. In addition, Xilinx and its Alliance ecosystem are continuously expanding market-specific C libraries such as OpenCV for video and image processing and Machine Learning for Automotive Driver Assistance Systems (ADAS) and Data Center applications. Xilinx’s new LogiCORE IP subsystems are highly configurable, market-tailored building blocks that integrate up to 80 individual IP cores, software drivers, design examples, and test benches. New IP subsystems are available for Ethernet, PCIe, video processing, image sensor processing, and OTN development.  These IP subsystems are based on industry standards such as AMBA AXI 4 interconnect protocol, IEEE P1735 encryption and IP-XACT to enable interoperability with Xilinx and Alliance member IP and to accelerate integration.

The combination of C-based IP and pre-packaged IP subsystems are rapidly combined leveraging Vivado IP Integrator for integration automation.  Vivado IPI’s integration automation provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability. The platform aware intelligence, can preconfigure the Zynq SoCs and MPSoCs processing system with the correct peripherals, drivers, and memory map to support the target board. Design teams can now rapidly identify, reuse, and integrate both software and hardware IP, targeting the ARM® processing systems and high-performance FPGA logic.

“HLx Editions provide a framework for creating and programming reusable All Programmable platforms,” said Tom Feist, senior director of Design Methodology Marketing at Xilinx. “By providing the advanced tools, IP and UltraFast Design Methodologies in all of our Vivado packages, our mainstream customers can focus on their differentiated value and get even better designs faster.”

HLx Complements SDx for Creating and Deploying Platforms

HLx speeds the creation, modification, and programming of All Programmable platforms for hardware engineers, complementing the Xilinx SDx Development Environments (SDSoC, SDAccel and SDNet) which are tailored for software and systems engineers. The SDx family of development environments enables software-defined programming of HLx generated platforms using a mix of C, C++, OpenCL, and the emerging P4 language for packet processing.  HLx and SDx represent Xilinx’s new era of design enablement solutions for developing smarter, connected and differentiated systems leveraging a new era of All Programmable devices including Zynq SoCs, MPSoCs, ASIC-class FPGAs and 3D ICs.


The Vivado Design Suite HLx Editions upgrades are now available in the Vivado Design Suite 2015.4 release supporting Xilinx 7 series, UltraScale, and UltraScale+ devices.

To learn more watch the Vivado QuickTake Videos, sign up for training, and take advantage of the UltraFast Design Methodology Guide for Vivado Design Suite and the new UltraFast High-Level Productivity Design Methodology Guide for the Vivado Design Suite.


BiS Team

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